For now, Bizen may open the door to logic production in older fabs. If it can be adopted by the industry, it may be possible to set back the Moore’s Law clock by 10 years or more, given the advantage of making the Bizen die area smaller than that achieved by CMOS logic at a given technology node.
Traditional transistors are under heavy pressure
Transistors on chips have gotten smaller, faster, and cheaper for decades, but in recent years, Moore’s Law is facing a failure.
Smaller, faster new transistors will once again enable the computer industry to make great strides. In this way, Moore’s Law may soon be brought back to life, and computer performance is expected to grow exponentially.
Transistors are increasingly developed, and to push the physical limits, traditional methods are no longer applicable. Today, innovative methods must be used to manufacture transistors.
Realistic challenges faced by process upgrades
In the past, the focus of the semiconductor market has revolved around traditional chip scaling, adding more functionality to a device and then shrinking the device at each process node.
In recent years, however, scaling chips at each node has become more expensive and complex, and today only a few people can afford to design chips at advanced nodes.
The chip industry is highly sensitive to numbers, and has increasingly become a curse for foundries and chip manufacturers. For the giants at the top of the pyramid, there are no exceptions.
The more advanced the process, the smaller the area, and the power consumption will be reduced while the performance is improved. Generally speaking, 10nm vs. 16nm, the power consumption will be reduced by about 20% to 30%. The smaller the number, the more advanced the technical level is.
But whether it is a chip manufacturer or a wafer foundry, the more it goes on the road of upgrading, the more pressure it bears. Among the top four pure-play foundries in the world last year, in addition to TSMC, GlobalFoundries, UMC and SMIC saw their average revenue per wafer decline.
In the next five years, only TSMC, Samsung and Intel will be able to invest in wafer foundries with advanced manufacturing processes. Under the fierce competition, pricing pressure will surely continue until 2022.
Multiple consumption of traditional structure
A depletion region is formed at the interface of the polysilicon and gate oxide, and as the device continues to shrink, the polysilicon depletion becomes larger, and a larger portion equivalent to the oxide thickness will limit the gate oxide capacitance. The negative effect of multivariate depletion is due to the reduction of the charge density of the inversion layer and the degradation of device performance.
With conventional structures, as the channel length shrinks, the gate does not fully control the channel, which is undesirable. One of its effects is causing more subthreshold leakage from drain to source, which is not very good from a power consumption perspective, the gate cannot control the leakage path away from it, doping is inserted into the channel to reduce various SCEs .
New quantum tunneling transistor is born
British foundry Semefab has produced samples of a new quantum tunneling transistor and wafer process called Bizen that can dramatically reduce lead time, wafer area and process layers while increasing speed, reducing power consumption and improving CMOS performance. gate density.
Bizen is a new transistor architecture developed by Nottingham, UK-based startup Search For The Next (SFN) that uses quantum tunneling instead of an insulated gate. This structure, which consists of a combination of bipolar and Zener diodes, allows logic to be produced in only 8 layers in standard CMOS processes, compared to 20 to 30 layers required for conventional CMOS transistor designs.
The Bizen test chip produced by Semefab in Glenrothes, Scotland, with a 1μm process technology, shortens the lead time of traditional CMOS transistor designs from 15 weeks to 3 weeks, and the chip area is one-third the size of similar CMOS devices under the same process.
The essence and application of Bizen structure
Bizen is a novel transistor structure, essentially a PNP device whose base is driven through a quantum tunnel junction and includes a self-biased transistor inside a second tunnel junction. Currently, this structure is based on silicon, but has the ability to migrate to GaN and other compound semiconductors.
Quantum tunneling technology is nothing new, it has been widely used in NOR flash memory chips. However, in the past two years, the technology has been applied to logic devices with Bizen, and has been produced and verified by Semefab.
With careful modeling, traditional horizontal and vertical bipolar structures can be integrated into Bizen without additional process complexity, showing that it does have the potential to disrupt the industry.
Although CMOS is prone to latch-up and ESD, defectivity is not a big deal for CMOS, and CMOS’s low power consumption has passed the test of time and is generally reliable.
But CMOS is complex, and even more so when integrated with power, and complexity means longer lead times and higher costs, and Bizen addresses these issues.
Bizen transistor structure has outstanding advantages
Bizen’s transistors have a PNP-like structure, but with a different base. This is a bipolar mechanism, not a unipolar mechanism like a MOSFET. It is not in direct contact with the base like a BJT and is not isolated by oxide like a MOSFET.
Instead, a tunnel junction to the base, which is heavily doped, allows Bizen—a bipolar regulator—to retain the advantages of conventional bipolar processing, but eliminate the drawbacks by using a Zener quantum tunneling mechanism.
Although Bizen’s two electrodes are also referred to as “collector” and “emitter,” the structure is actually symmetrical, and the two terminals can be swapped without changing the function.
The second tunnel junction biases the Bizen so that it is “on” but not saturated when the tunnel terminals are open. While this represents a continuous current flow to ground during operation, the tunneling current is typically only 2nA – 5nA, a low power “sleep” mode can be introduced by including a single structure that disconnects the bias tunnel.
Any logic built using Bizen transistors is current-based logic, not voltage-based logic, and requires no additional space-consuming current sinks other than resistors or bias tunnel junctions.
Arbitrary logic functions can be implemented using Bizen transistors, and logic chips can be implemented with only 4 process lithography masks instead of 8 masks for the entire process because transistor-to-transistor connections can be made inside the transistors.
Bizen’s dynamic power is much lower because it doesn’t have all the power-wasting MOSFET gate capacitances associated with CMOS. Current methods allow for analog calculations, where currents can merge and grow over time. The chip can be divided into 8 layers without using an SOI substrate.
The advantages of tunneling transistors are becoming more and more obvious
Transistors are the basic building blocks of Electronic devices, and for the past 40 years, scientists have mainly increased the computing power of electronic devices by integrating more transistors onto a single chip, but this road seems to be coming to an end.
The industry believes that the semiconductor industry is rapidly approaching the physical limits of transistor miniaturization, and the main problem with modern transistors is excessive heat generation.
Electron tunneling devices have a long history of commercialization, and the principles of quantum mechanical tunneling have also been used in data storage devices. With the latest technology, a USB flash memory device may have billions of TFET devices in the future.
Replacing current transistor technology with tunneling transistors does not require major changes to the semiconductor industry, and much of the existing circuit design and circuit manufacturing infrastructure can continue to be used.
CMOS process is still the best way to promote miniaturization in the short term
To keep Moore’s Law alive, the only focus is on increasing transistor densities to consistently deliver better performance and energy efficiency performance.
As long as the industry can keep putting more transistors with better energy efficiency into smaller chip spaces, Moore’s Law will continue to survive, regardless of the method used to achieve this continued increase in transistor density.
Under this circumstance, in order to continue to promote Moore’s Law in the short term, it is still necessary to rely on the continuous introduction of more advanced CMOS process technology, so that the wafer manufacturing side can mass-produce transistors with smaller gate lengths. Taking TSMC as an example, the current progress is to etch 7nm transistors and move towards a 5nm process.
Each generation relies on the continuous scaling and evolution of the global semiconductor process, which drives the continuous scaling of transistor density, so as to introduce better performance and power consumption, and meet the higher computing needs of the new technology wave, thus forming the current global technology industry supply chain status, and Create an increasingly technologically permeated social environment.
As the mobile era has gradually matured and its growth has gradually slowed down, artificial intelligence + 5G will be the main driving force for the advancement of semiconductor process miniaturization in the next stage.
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