What has chip manufacturing gone through in order to be smaller, faster, and more power efficient?

Every few months, newer Electronic products come out. They are typically smaller, smarter, run faster and have more bandwidth, and are more power efficient, all thanks to a new generation of advanced chips and processors.

What has chip manufacturing gone through in order to be smaller, faster, and more power efficient?

Every few months, newer electronic products come out. They are typically smaller, smarter, run faster and have more bandwidth, and are more power efficient, all thanks to a new generation of advanced chips and processors.

Entering the digital age, we are as confident that new devices will continue to be introduced as we believe the sun will rise tomorrow. Behind the scenes, engineers actively work on semiconductor technology roadmaps to ensure the next-generation chips needed for new devices are ready.

For a long time, chip advancements were made by shrinking the size of transistors so that more transistors could be made on a single wafer, doubling the number of transistors every 12-24 months— This is known as “Moore’s Law”. Over the years, to keep pace with the times, the industry has seen many major innovations, including copper/low-k interconnects, new transistor materials, multiple patterning schemes, and three-dimensional (3D) architectures.

The shift to developing 3D structures presents new challenges, which intensify as aspect ratios increase. As you may have imagined, 3D architectures require fundamental changes in device design, requiring new materials, new deposition and etching methods to achieve. In this article, we will take you through the important milestones in the semiconductor industry’s realization of 3D architecture.

Preparation stage: plane craft

Creating integrated circuits was initially a two-dimensional problem: take a flat silicon wafer, place various structures on the surface, and connect them with wires. This is done by depositing layers of material, patterning them using photolithography, and etching the necessary features in the exposed areas. This was a huge breakthrough for the electronics industry.

As technology needs continue to evolve, more circuits need to be built in tighter spaces to support smaller structures. What used to be relatively straightforward processes has become increasingly complex.

3D structures are becoming increasingly attractive as the cost of creating 2D structures continues to increase and viable methods for scaling them in 2D planes are exhausted. The semiconductor industry began developing early selective etch applications to support 3D technology more than a decade ago, and has continued to expand, from packaging to non-volatile memory and even the transistors themselves.

What has chip manufacturing gone through in order to be smaller, faster, and more power efficient?

Transistors go 3D

The workhorses of many electronic systems are transistors. In the past, transistors have been flat structures whose characteristics are determined by the width and length of the transistor channel. Transistor performance is controlled by gates placed on the channel, but this provides only limited control because the other side and bottom of the channel are not controlled.

The first step in moving from planar to 3D is to design a fin for the channel, which can be controlled by grids on three sides. However, for optimal control, access to all four sides of the transistor is required, leading to the development of gate-all-around (GAA) transistors. In the GAA structure, multiple wires or sheets are stacked on top of each other, and the gate material completely surrounds the channel.

What has chip manufacturing gone through in order to be smaller, faster, and more power efficient?

Flash boost

The shift to 3D was applied to NAND flash as early as 10 years ago, when horizontal strings of memory bits were stacked upwards.

Vertical structures are made of alternating thin layers of material and stacks of as many process layers as possible. When building such a structure, special care is required in at least two respects: first, each layer must be uniform in thickness and very flat so that the bits in each layer are the same size as the other bits; They must be connected to each other – this requires building a stack and drilling holes in the stack by etching, then filling the holes with the appropriate connecting material to complete the structure. Among them, both the etching and deposition processes are extremely challenging and require precise execution.

These challenges limit the number of layers in the stack, so new approaches are needed to increase the number of layers.

What has chip manufacturing gone through in order to be smaller, faster, and more power efficient?

Looking to the future: 3D DRAM

The physical mechanism of dynamic random access memory (DRAM) is completely different from that of 3D NAND, and the method used has also been completely changed.

DRAM requires high-capacity capacitors, which is a challenge for precise construction in 2D arrays. Vertical stacking is more difficult and requires more R&D to find economical ways to stack the dielectric and active silicon together. Lithography may need to affect multiple layers simultaneously – there is no mass production process yet.

3D packaging is gaining popularity

The chips are packaged and placed on a printed circuit board (PCB). In the past, encapsulation was just to protect the fragile silicon chip and connect it to the circuit board. Today, packages often contain multiple chips, and as the need to shrink chip footprints increases, packaging is also moving to 3D.

3D packaging requires chips to be stacked, which involves dense connections between chips — connections that increase signal speeds because they’re much shorter and can carry more signals simultaneously. However, in stacks of more than two chips, some of these signals also need to be connected to chips higher in the stack through conductive channels known as “through-silicon vias” (TSVs).

What has chip manufacturing gone through in order to be smaller, faster, and more power efficient?

An important end-market application for 3D chip stacks has been in the memory space—high-bandwidth memory (HBM) is the most common. Memory chips can also be stacked onto CPUs or other logic chips to speed up fetching data from memory.

Today, 3D is a must for miniaturization

Considering 3D has become standard practice when addressing all the scaling constraints in semiconductor manufacturing. While 3D may not be the answer to every problem, it’s especially useful in the aforementioned applications.

Every new application is accompanied by the difficult problem of how to build it, which requires innovative thinking and continuous development in the field of silicon process. Semiconductor manufacturing equipment is the main driver of the continuous realization of 3D structure in the chip industry.

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