“Embedded systems are “devices used to control, monitor, or assist the operation of equipment, machinery or plants” (devices used to control, monitor, or assist the operation of equipment, machinery or plants). It can be seen that the embedded system is a combination of software and hardware, and can also cover auxiliary devices such as machinery.
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Embedded systems are “devices used to control, monitor, or assist the operation of equipment, machinery or plants” (devices used to control, monitor, or assist the operation of equipment, machinery or plants). It can be seen that the embedded system is a combination of software and hardware, and can also cover auxiliary devices such as machinery. At present, a generally accepted definition in China is: a dedicated computer system that is application-centric, based on computer technology, can be tailored by software and hardware, and adapts to the strict requirements of application systems for function, reliability, cost, size, and power consumption. The embedded system must tailor the software and hardware according to the application requirements to meet the requirements of the function, reliability, cost and volume of the application system. Therefore, if a relatively general software and hardware foundation can be established, and then a system adapted to various needs can be developed on it, which is a better development model. The core of the current embedded system is often a microkernel with only a few K to dozens of K, and functions need to be expanded or reduced according to the actual use. However, due to the existence of the microkernel, this expansion can be carried out very smoothly.
With the wide application of embedded systems, the demand for serial communication in the system is getting higher and higher, and the protocols for serial data transmission are also diversified. Commonly used are SSI, SPI, I2C, UART, etc. SSI (Server Side Include), commonly known as Server Side Include, is a server-based web page creation technology similar to ASP. Most (especially based on Unix platforms) WEB servers such as Netscape Enterprise Server support SSI commands. In addition, in the field of computer hardware, SSI is the English abbreviation of Synchronous Serial Interface (Synchronous Serial Interface). In addition to being used for general serial data transmission, the SSI interface in the microprocessor MCF5329 supports two audio bus interfaces (I2S and AC97 interfaces) due to its frame synchronization signal that can be used for synchronization of left and right channel data. , The microprocessor uses a central processing unit composed of one or a few large-scale integrated circuits. These circuits perform the functions of control components and arithmetic logic components. Compared with the traditional central processing unit, the microprocessor has the advantages of small size, light weight and easy modularization. The basic components of the microprocessor are: register file, arithmetic unit, timing control circuit, and data and address bus. The microprocessor can complete operations such as fetching instructions, executing instructions, and exchanging information with external memory and logic components, and is the operation control part of the microcomputer. It can form a microcomputer with memory and peripheral circuit chips.
TLV320DAC23 is a high-performance stereo high-end codec chip launched by TI. It supports multiple sampling rates and multiple audio formats, and has the characteristics of low power consumption and small package. It is widely used in portable digital audio processing systems.
1 The working principle of synchronous serial interface SSI
Synchronous SerialInterface (SSI) is a full-duplex serial interface that allows the chip to communicate with a variety of serial devices. Text, graphics, or application information can be included into web pages using the Server Side Include (SSI) directive. For example, SSI can be used to include time/date stamps, copyright notices, or forms for customers to fill out and return. Using include files is a convenient way to have text or graphics that recur in multiple files. Instead of having to enter the content into all files, it is sufficient to put the content in an include file. The include file is invoked with a very simple statement that instructs the web server to insert the content into the appropriate web page. Also, when using include files, all changes to the content can be done in just one place. The SSI module structure is shown in Figure 1.
As can be seen from the figure, the SSI module consists of a transmitting circuit, a receiving circuit, a serial clock and a frame synchronization clock generating circuit. The transmitting circuit and the receiving circuit are independent of each other, but share the serial clock and the frame synchronization clock.
1.1 SSI module pin signal description
SSLCLKIN: SSI clock input signal.
SSLBCLK: SSI serial bit clock.
SSLMCLK: SSI serial master clock signal, in SSI master mode,
This signal also acts as the oversampling clock signal.
SSI_FS: SSI serial frame synchronization signal.
SSLRXD: SSI serial receive data signal.
SSI_TXD: SSI serial transmit data signal.
1.2 Operating Modes of SSI
SSI has 3 basic synchronous operation modes: normal mode, network mode and gate clock mode.
The normal mode is the simplest mode, only one word can be transmitted in a frame, and each frame needs a frame synchronization signal to control the synchronization; the network mode is mainly used in the case of multiple time slots, and 2 words can be transmitted in a frame to 32 words vary; in gate clock SSI_BCLK mode, the serial bit clock SSI_BCLK indicates valid data on the transmit or receive pins.
In addition to the above three basic modes, for audio applications, SSI also supports two derivative modes – I2S mode and AC97 mode, which are used to transmit I2S and AC97 audio format data respectively.
1.3 Initialization of SSI
Correct sequence to initialize SSI modules:
①Power on or restart SSI (SSI_CR[SSI_EN]=0), that is, close the SSI module function.
②Configure the SSI module. The involved registers include control register SSI_CR, interrupt enable register SSI_IER, transmit configuration register SSI_TCR, receive configuration register SSI_RCR and clock control register SSI_CCR.
③ Set the necessary interrupt or DMA through the SSI_IER register.
④Set SSI_CR[SSI_EN]=1 to allow SSI module function.
⑤Set SSI_CR[TE/RE]to start sending/receiving data.
1.4 The working process of SSI
(1) Send data
In the case of single channel, the data is transmitted from the serial transmit data register SSI_TX0 to the transmit shift register TXSR, and then sent out through the serial transmit pin SSI_TXD, and then decides whether to generate a transmit interrupt according to user settings. If the transmit buffer TXFIFOO is allowed, SSI_TX0 continues to take data from TXFIFOO until all the data in TXFIFOO is sent, and then decides whether to generate a transmit interrupt through user settings. In the case of dual channels, the transmission shift register TXSR takes out data alternately from SSI_TX0 and SSI_TX1.
(2) Receive data
In the case of single channel, the data comes in from the serial receive pin SSI_RXD, and is transferred from the receive shift register RXSR to the receive data register SSI_RX0, and then decides whether to generate a receive interrupt according to the user settings. If the receive buffer RXFIFOO is enabled, SSI_RX0 writes data to RXFIFOO and continues to fetch data from the receive shift register. In the case of dual channels, the receive shift register RXSR transfers data to SSI_RX0 and SSI_RX1 alternately.
2 Introduction to Audio Codec Chip
The main function of the Codec codec is to compress and decompress the video signal. The computer industry defines true color through a 24-bit measurement system, which defines nearly a million colors, approaching the limits of human vision. Now, the most basic VGA Display has 640*480 pixels. This means that if the video needs to be played at 30 frames per second, up to 27MB of information is transferred per second, and a 1GB hard drive can only store about 37 seconds of video information. Therefore, the information must be compressed. By discarding some digital information or image information that is easily ignored by our eyes and brains, the information content of the video is reduced. The software or hardware that compresses and decompresses video is the codec. The compression ratio of the codec ranges from 2:1 to 100:1 in general, making it possible to process large amounts of video data.
TLV320DAC23 is a TI company
A high-performance stereo audio processing chip (CODEC chip) launched, using multi-bit sigma-delta oversampling technology, the sampling rate can be from 8 kHz to 96 kHz, and the transmission word length can be selected as 16-bit, 20-bit, 24-bit or 32 bits; the maximum output signal-to-noise ratio can reach 100 dB; the control port is compatible with SPI, 2-wire and other protocols; the power is 18 mw in playback mode, and less than 15 μW in power saving mode; suitable for portable digital audio processing. Its functional module block diagram is shown in Figure 2.
2.1 Control Interface
The control interface is used to program the registers of the device TLV320DAC23 and set the working parameters of the audio chip. It is compatible with two modes: SPI three-wire mode and 2-wire mode.
MODE: Mode selection pin. When it is 0, the 2-wire mode is used; when it is 1, the SPI mode is used.
SCLK: Control port serial data clock.
SDI: Control port serial data input.
CS: Control port input latch/address selection. In SPI mode, CS is used for data latch control; in 2-wire mode, CS defines the seventh bit of the device address field. In SPI mode, a control word is 16 bits, divided into two parts: the upper 7 bits are the control address, and the lower 9 bits are the control word. The 16-bit control word is transmitted from the MSB bit, each bit is latched on the rising edge of SCLK, and the entire 16-bit control word is latched into TLV320DAC23 by CS at the lowest bit.
The working principle of synchronous serial interface SSI and its application in audio processing
2.2 Analog Interface
Analog interfaces include line-in, line-out, and headphone-out. The headphone output can drive 16Ω or 32Ω headphones with a volume gain of 6 dB to a 73 dB.
LLINEIN, RLINEIN: Left and right channel input.
LOUT, ROUT: Left and right channel output.
LHPOUT, RHPOUT: left and right channel headphone output
2.3 Digital Audio Interface
The digital audio interface is used to input the D/A data of TLV320DAC23.
BCLK: I2S serial bit clock. BCLK is an output in master mode, and BCLK is an input in slave mode.
DIN: I2S serial data input.
LRCIN: word clock signal (frame signal), used to control the data of the left and right channels. In master mode, the signal is generated by the TLV320DAC23, and in slave mode, the signal is generated by the master device (such as a DSP or MCU).
TLV320DAC23 supports 4 audio interface modes: right-justified mode, left-justified mode, I2S mode and DSP mode. These 4 modes are MSB first, with different word lengths from 16 to 32 bits (except for right justification, which does not support 32 bits). Figure 4 is the digital audio interface timing in I2S mode. The MSB of the data starts to transmit on the second BCLK rising edge after the falling edge of LRCIN.
2.4 Clock Interface
MCLK: chip master clock signal. When the TLV320DAC23 is used as the master device, the signal is generated by the chip itself; when the TLV320DAC23 is used as the slave device, the signal is generated externally.
CLKOUT: Clock output signal. Can be MCLK or MCLK/2.
3 Audio driver design based on MCF5329
3.1 Hardware circuit
There are two interfaces between TLV320DAC23 and MCF5329: one is the control interface, which is used to set the register of TLV320DAC23 to set its working parameters. Because MCF5329 has QSPI module, it is compatible with SPI interface format, so the control interface of TLV320DAC23 adopts SPI mode. The other is a digital audio interface, which is used to transmit the audio data of the TLV320DAC23 and control the timing of the data.
In this design, the clock signal is provided by the microcontroller MCF5329, so MCF5329 is set as the master device, and TLV320DAC23 is used as the slave device. The specific connection is shown in Figure 5.
3.2 Software Design
The process of audio playback is as follows: the program detects that the user space has audio data that needs to be played, and then copies the audio data to the established buffer; then transfers the audio data in the buffer to the send pin SSI_TXD of the SSI module through DMA, The send pin sends the data to the TLV320DAC23 and plays it out through the headphones.
The software design process is shown in Figure 6. Among them, the audio buffer is set as a fixed-size circular queue, and its setting is shown in Figure 7. Initially, bufstart, audiostart, and audiotail all point to the buffer header. When there is data in the user space, copy the data to the buffer and use audiotail to indicate the tail of the data, and the head of the data is connected to the SSI_TXD pin through the DMA engine.
Epilogue
This paper analyzes the working principle and process of the synchronous serial interface SSI, and introduces the application of SSI in audio processing in detail through the communication with the codec chip TLV320DAC23. Practice shows that the SSI interface is simple, flexible and reliable to use.
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