[Introduction]I believe that all engineers and friends have encountered the phenomenon of unstable power supply. This phenomenon may be caused by improper schematic diagram or PCB design, or it may be caused by insufficient loop compensation; and due to sub-harmonic oscillation How much do you know about the instability of the power supply?
I believe that all engineers and friends have encountered the phenomenon of unstable power supply. This phenomenon may be caused by improper schematic diagram or PCB design, or it may be due to insufficient loop compensation; Stability phenomenon, how much do you know?
There are two types of closed-loop feedback control of switching converters commonly used: voltage mode control and current mode control. The voltage-based PWM control technology refers to the error signal Verror obtained after the output voltage Vout is compared with the reference voltage Vfb. The error signal is compared with the sawtooth wave signal generated by the sawtooth wave generator, and then the PWM comparator outputs a square wave drive signal with a changing duty cycle. The biggest disadvantage of this loop is that the current of the switching power supply will flow through the Inductor, resulting in a certain delay in the corresponding voltage signal.
Based on the above shortcomings, more and more power supply manufacturers will add current feedback PWM control mode when designing products, and the current control mode is divided into peak current control mode and average current control mode. Compared with the peak current control mode, the average current control mode has a slower response speed and a more complex control loop, so the peak current control mode is more common in practical applications. This article will focus on the power supply loop in peak current control mode, and take ADI’s power supply as an example to illustrate the current practices of related manufacturers in chip design.
The following figure (Figure 1) is a brief schematic diagram of the peak current control mode and the waveform diagram of the key signal
Figure 1 Schematic diagram of peak current control mode and waveform diagrams of key models
The working process of peak current control:
First, Ra and Rb sample the output voltage, and get the control voltage Vc after compensation by the error amplifier. The Vc voltage is used as the inverting input of the comparator, and the high-side current sampling is used as the non-inverting input. When the value of the high-side current multiplied by Rsense reaches the control voltage Vc, the Mos signal is turned off, and the switch signal is reset at the next clock frequency; the main function of the peak current control mode is to keep the peak current of the switch tube constant.
The peak current PWM control mode has strong load adjustment ability and input anti-interference ability, and it is easy to realize current limiting or overcurrent protection, but the peak current control mode has a disadvantage. When the duty cycle is greater than 50% and in CCM mode, If there is a small fluctuation in the inductor current in the previous cycle, the fluctuation will increase in the next cycle, so after N cycles, the PWM duty cycle will be larger or smaller, which is what we call subharmonics. wave oscillation.
Below we explain this phenomenon based on the theory:
Figure 2. Schematic diagram of duty cycle less than 50% in peak current control mode
As shown in the figure above (Figure 2), when the duty cycle is less than 50% in the peak current control mode, m1 is the rising slope of the inductor current when the switch is turned on, m2 is the slope of the inductor current falling when the switch is turned off, and is the fluctuation of the inductor current affected by the outside world in the previous cycle, and is the error generated in the next cycle, the expression is:
(m2 In theory, m2
Figure 3, schematic diagram of duty cycle greater than 50% in peak current control mode
As shown in the figure above (Figure 3), when the duty cycle is greater than 50% in the peak current control mode, the expression for the inductor current fluctuated by the input disturbance is:
At this time, m2>m1, after several cycles, the result is in a divergent state, and the offset will become larger and larger. In response to this feedback, PWM will adjust the duty cycle, and the duty cycle will be larger and smaller;
How to deal with sub-harmonic oscillations in peak current control mode?
The current common practice is to use the sawtooth wave current compensation technology. After Rsense, compare with the newly generated pulsating ramp signal to invert the comparator;
Figure 4. Peak current control mode after adding slope compensation
As can be seen from the above figure (Figure 4), adding a slope with a slope of -m to Vc, the expression for the inductor current fluctuated by the input disturbance at this time:
Before compensation: After compensation:
Our purpose is to make the expression tend to converge after compensation, and the value of m is usually as long as m>0.5*m2, which can ensure that it tends to converge after compensation;
Based on the sub-harmonic oscillation problem in the peak current control mode explained above, some engineer friends may wonder, it seems that this problem is rarely encountered in daily research and development?
Mainly because in the current IC design, slope compensation is usually integrated into the chip, which greatly reduces the difficulty for engineers to add compensation through peripheral hardware circuits.
Figure 5, the internal block diagram of ADP2386, the slope compensation part is in the red box
We take ADI’s ADP2386 as an example to analyze how the peak current control mode works under slope compensation: First, the inductor current collected by Rsense is amplified by the error amplifier Acs, added to the slope compensation, and sent to the positive port of the comparator, the FB pin After comparing with the Reference, it is sent to the negative end of the comparator, and then the control signal is given through the comparison between the two to complete the entire loop control.
Is the slope compensation coefficient m the bigger the better? No, because the switching power supply has its own loop bandwidth, which is usually used to measure the dynamic response of the loop. When m increases, the phase curve of the loop Bode diagram of the switching power supply will be improved, and the resonance of the gain curve will be improved. Peaks are also suppressed. However, the resulting problem is the reduction of the loop bandwidth and the reduction of the dynamic response, so the compensation coefficient is not as large as possible. The appropriate slope compensation coefficient m should take into account the stability and the dynamics of the loop.
Through the above study, I believe that everyone has initially mastered the peak current control mode and the sub-harmonic oscillation that may be brought about by it. Although the vast majority of IC manufacturers have helped us solve this problem when designing chips, it is of great benefit to our research and development of power supplies to have a deep understanding of the principle and processing method of subharmonic oscillation. For more detailed technical guidance, you can contact the local offices of Junlong Technology. The technical staff of Junlong Technology is willing to provide you with more detailed technical support.
1. ADP2386 | Internal Power Switching Buck Regulator | Analog Devices (analog.com)
2. Principle and Design of Switching Power Supply Zhang Zhansong Edition Electronic Industry Press
(Source: Junlong Technology, Author: Lu Cong)