Structure and working principle of integrated DC/DC converter

For smart card power supply, this paper proposes an integrated DC/DC converter structure and analyzes its working principle. The system can achieve 85% efficiency, is robust enough to meet all complex ISO7816-3 specifications, and has passed EMV and EMV Co program levels 1 and 2. This structure is particularly suitable for smart card applications such as portable cash registers (POS).

For smart card power supply, this paper proposes an integrated DC/DC converter structure and analyzes its working principle. The system can achieve 85% efficiency, is robust enough to meet all complex ISO7816-3 specifications, and has passed EMV and EMV Co program levels 1 and 2. This structure is particularly suitable for smart card applications such as portable cash registers (POS).

Structure and working principle of integrated DC/DC converter

The operating voltage of the smart card has been upgraded to be suitable for any chip specially designed for this application. The original ISO7816-3 and EMV (Europay/Master card/Visa) files now include 1.8V, 3.0V and 5.0V as applicable operating power sources. Therefore, the physical interface between the card and the main MPU must be able to adapt any of the above power supplies. The power supply must maintain the operating conditions specified in Table 1. In addition, the power supply must be able to disconnect the card within 750μs, especially when the card is removed with power on.

In addition to quiescent operation, the power supply can keep the output voltage within tolerance under a load of 100mA/400ns pulses. Such requirements relate to the state of the system, not just the power supply.

DC/DC converter

Structure and working principle of integrated DC/DC converter

As applications grow, from battery-powered portable systems to TV satellite receivers, smart card interfaces must efficiently handle a large input voltage range with high efficiency. Basically, it can be implemented in any type of configuration as long as the required power is supplied to the card. For example, it can be designed as a switched capacitor based converter, but its limited efficiency becomes a key issue when considering portable POS systems. This is different for GSM applications, where the output power is limited to 50mW, so this capacitor-based structure is preferred on the radiotelephone PCB to save space.

Considering that energy saving is a key issue for POS portable modules, Inductor-based structures are prioritized to maximize efficiency. In fact, at output powers up to 300mW, the efficiency of the inductor structure can reach 85% over the entire operating voltage range, a level that is difficult to achieve with low-cost switched capacitor technology.

On the other hand, since the input voltage can go from as low as 2.70V to as high as 5.50V (either when the battery is near empty or after the battery is charged), the structure must automatically and without adjustment switch from boost to buck operation and vice versa . The concept depicted in Figure 1 has been developed to meet these requirements, with maintaining EMV as the primary goal in the design.

A real system implemented in a silicon die is more complex, since it operates without voltage spikes while still achieving regulation and low ripple. It is important that the circuit meets all EMV specifications, especially the power-down sequence, power-off sequence, and output short-circuit current.

To meet these requirements, the converter shown in Figure 2 adds several additional NMOS and PMOS transistors.

The system operates on a two-cycle concept (see Figures 2 and 3 for all notes), with a special structure that takes into account smart card requirements:

Cycle 1: Q1 and Q4 are turned on, and inductor L1 is charged by an external battery. At this stage, Q2/Q3 and Q5/Q6 are turned off.

The current through the two MOSFETs, Q1 and Q4, is monitored internally and turns off when the Ipeak value (peak current, depending on the programmable output voltage value) is reached. At this point, cycle 1 completes and cycle 2 begins. The “on” time is a function of the battery voltage and the value of the inductor network (L and Zr) connected between pins 10 and 11.

To prevent uncontrolled operation, a 4µs pause structure ensures that the system operates only within a continuous cycle 1 loop during overload or low battery input conditions.

Cycle 2: Q2 and Q3 are turned on, and the energy stored in the inductor L1 is transferred to the external load through Q2. At this stage, Q1/Q4 and Q5/Q6 are turned off. The current flow period is a constant value of 900ns (typ), and if the CRD_VCC voltage is lower than the specified value, cycle 1 is repeated after this time.

When the output voltage reaches the specified value (1.80V, 3.0V or 5.0V), Q2 and Q3 are turned off immediately to avoid overvoltage on the output load. At the same time, two additional NMOSs, Q5 and Q6, are turned on to completely drain the current stored in the inductor, avoiding ringing and voltage spikes on the system. Figure 3 shows the theoretical waveforms of the DC/DC converter.

When CRD_VCC is programmed to 0V, or when the smart card is removed from the socket, the active pull-down Q7 rapidly discharges the output storage capacitor, ensuring that the output voltage is below 0.40V when the card is slid over the ISO contacts. Due to the low on-resistance of Q7, the output voltage drops rapidly to 400mV in less than 100μs, far below the maximum value of 750μs specified by EMV.

Output voltage ripple, although not directly specified by ISO7816-3 or EMV, plays an important role in the operation of smart cards. Its peak-to-peak value depends on the following two main electrical parameters:

1. The total series resistance between the output silicon structure and the net storage capacitor;

2. Regulation, the ability to sense output voltages with small thresholds and hysteresis.

These parameters depend on the internal bonding wires that connect the chip to the outside world, the pin contacts that connect the series resistors of the storage capacitors, and the printed copper wires that connect the pins to the load. Multi-bond wire technology is widely used to reduce the series resistance to 50m (or lower resistance if a wider wire is used when high current is passed through the pins.

The width of the printed circuit board traces can be based on the current handling needs required for a given application. Additionally, this series resistance can be a problem because the external passive components involved vary widely from application to application. The key part is the energy storage capacitor, as (for economic reasons) are generally low cost types, but again this creates high voltage spikes that are almost impossible to completely eliminate.

Depending on the type of technology used to develop the capacitance, the parasitic elements may have relatively high values, producing large uncontrollable spikes. As shown in Figure 4, this equivalent series resistance (ESR) is very prone to such spikes because the supply current flows directly through it and brings high voltage pulses into the output source.

Based on the experiments performed in the characterization of the NCN6001 and NCN6004A, the best solution is to use two 4.7μF/10V/ceramic/X7R capacitors in parallel for CRD_VCC filtering. ESR does not exceed 50m over the entire temperature range? , and the combination of standard components provides an acceptable -20% to +20% tolerance with limited cost increase. Table 2 provides a rough comparison of commonly used capacitor types. Figure 5 shows the CRD_VCC ripple observed on the NCN6001 or NCN6004A demo board for different capacitor types for output voltage filtering. The large and fast transients observed on the above curve are very difficult to filter out because of their high energy. Clearly, aluminum capacitors are not suitable for this type of application and should be avoided.

The second parameter depends on the performance of the internal comparator, voltage reference tolerance and digital processing. The voltage reference is drawn from a stable bandgap circuit, resulting in a ±3% tolerance. On the other hand, the deviation and drift of analog functions are reduced by high-end integration techniques. A detailed analysis of the DC/DC operation helps to understand the effect of each component on the output voltage ripple (see Figures 2 and 6).

In operation, the inductor current alternates between Iv and Ip values, as shown in Figure 6. When the system inverts from cycle #1 to cycle #2, the energy accumulated in the inductor is transferred to the load, and the storage capacitor voltage increases as energy is transferred to it.

Let k=R1/(R1+R2). When Vo is greater than k*Vref, the internal comparator U1 flips, and the output current drops to zero at time t1. Correspondingly, the output capacitor is loaded with all the energy previously stored in the inductor, and the output voltage keeps increasing to the value specified by the parameter k*Vref The reference value above the final voltage Vohp represents the high side ripple amplitude.

At this point, the output voltage begins to drop (because there is no more energy coming out of the inductor), and the comparator flips when Vo is less than k*Vref, depending on the load-determined time t2. The DC/DC converter continues to operate in cycle #1, but the output voltage continues to drop because it takes more time to reach the Ip current value (time t3), and after the inductor starts charging from zero, it reaches the low end of the ripple amplitude at Volp , cycle #2 starts a new cycle. The waveform diagram of Figure 6 describes this mechanism.

Conclusion of this paper

A DC/DC converter with an efficiency of 85% under operating conditions was developed for powering smart cards and complies with all complex ISO7816-3 specifications. The system is robust enough to prevent system latch-up when the load changes rapidly from zero to peak, even when the battery is at either end of the input voltage range. Additionally, short-circuit current protection avoids any thermal runaway, as the overload current trip point decreases with increasing temperature. This structure has passed the EMV and EMV Co programs Level 1 and 2, including the EMV2000 protocol.

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