Robust Low-Side Gate Drive Circuit Design Guidelines

【Introduction】With the advent of the new energy era, new energy applications such as on-board chargers (OBC) and photovoltaic inverters (PV inverters) have brought about the rapid development of digitally controlled switching power supplies.

In the composition of the switching power supply, the gate driver acts as a bridge connecting the control stage and the power stage, which is very important to the normal operation of the system. In the new energy vehicle market, especially in the application of on-board chargers related to personal safety, the requirements for the reliability of gate drivers are getting higher and higher. Taking the low-side driver as an example, this article lists the potential failure risks in the gate driver and the corresponding design guidelines in order to improve the reliability of the gate driver.

At the same time, this article also introduces TI’s latest UCC27624, a dual-channel low-side gate driver, with a negative voltage withstand capability as low as -10V input port and a strong anti-current backflow capability, making the chip suitable for high noise and auxiliary power supply transformer drive Application scenarios; with 5A driving capacity and maximum 30V driving voltage, high-speed and low-latency switching characteristics. It can effectively drive power switches such as metal oxide semiconductor field effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs).

In the application case of UCC27524A-Q1, there are usually two failure phenomena:

1. There is no open or short circuit and abnormal impedance phenomenon on the peripheral pins of the chip, but OUTA and OUTB have no output;

2. The chip output pin OUTA or OUTB has a short circuit to ground, VDD power supply or low impedance;

Failure analysis results usually show damage to the internal logic circuit or output power stage of the chip, and the cause of these damages often points to the external application circuit design. The following article describes several common causes of failure and gives countermeasures:

Robust Low-Side Gate Drive Circuit Design Guidelines

Internal block diagram of UCC27524A-Q1

VDD noise and pulse

As mentioned earlier, the UCC27524A-Q1 has high drive capability and high-speed switching characteristics. Therefore, in the transient process when the power switch is turned on and off, a higher di/dt will be generated in the VDD bias voltage supply loop, and then the parasitic inductance in the line will be coupled to generate a voltage pulse. If the voltage pulse is too high, it may cause chip damage.

On the other hand, VDD supplies power to the internal circuits of the chip through the internal LDO. When the power supply noise of VDD is too large, it is easy to transmit the noise to the internal circuit, such as the logic control circuit, which will cause current spikes, increase the power consumption and stress of the internal circuit, and be easily damaged after long-term operation.

Robust Low-Side Gate Drive Circuit Design Guidelines

In response to the above two problems, a cleaner power rail can be obtained by:

1. Place the capacitor as close as possible to the VDD pin to reduce the parasitic inductance of the line;

2. The VDD pin needs two kinds of capacitors. On the one hand, a capacitor with a slightly larger value (such as 1uF) is required to stabilize the voltage and provide energy to the driver chip. On the other hand, considering the frequency characteristics of capacitors, large-capacity capacitors exhibit inductive properties at high frequencies due to materials and package size. Therefore, a small-capacity and small-package chip ceramic capacitor (such as 1uF) is also required to filter out high-frequency noise, and the small-capacity capacitor should be closer to the VDD pin.

Input negative voltage pulse

The drive input PWM signal is usually provided by the PWM controller or MCU, and these devices may be far away from the driver chip due to system limitations. On the other hand, there are similar problems in the placement of the drive and the power tube, so there is a certain parasitic inductance between the power ground, the drive ground and the control ground. As the power and switching speed of the switching power supply increase, the di/dt also increases rapidly. Coupled with the aforementioned parasitic inductance, there will be transient positive and negative voltage pulses at the levels between different grounds. Among them, after the driving input signal superimposes the ground plane pulse, there may be a spike that exceeds the withstand voltage of the input pin, thereby damaging the input stage of the driving chip.

Robust Low-Side Gate Drive Circuit Design Guidelines

In response to this problem, the design can be optimized by the following methods:

1. Increase the drive resistance, thereby reducing the switching speed and reducing the di/dt value of the power stage. However, this method increases the switching loss, especially with the increase of the switching frequency of the power stage, the switching loss accounts for a more and more significant proportion of the power consumption of the whole machine, so it is necessary to balance the design of the system requirements;

2. Optimize the layout, place the driver, power tube and controller as close as possible to reduce parasitic inductance;

3. Add an input RC low-pass filter network to the drive input pin to filter out relevant high-frequency noise. Choose an appropriate time constant to reduce input waveform distortion while attenuating noise at the target frequency as much as possible.

OUTx voltage pulse

Similar to the aforementioned risk of the input stage, the output stage of the driver chip will have positive and negative voltage pulses at the OUTx pin due to the line parasitic inductance and the high-speed drive current transient process. Fortunately, the built-in mosfet body diode of the output stage of the driver chip can freewheel the energy to ground or VDD when the voltage pulse is generated, thereby enhancing the voltage pulse withstand capability of the output stage to a certain extent. However, considering the large turn-on voltage drop of the body diode, the loss is high. Severe voltage pulses still run the risk of reducing chip life or even damaging the chip.

In response to this problem, the design can be optimized by the following methods:

1. Similar to the previous problem, optimize the layout and place the OUTx pin close to the gate of the power switch to reduce parasitic inductance;

2. Choose an appropriate clamp diode and place it close to the OUTx pin to absorb pulse energy and reduce the loss of the internal body diode;

3. Add a suitable bead to the OUTx pin to absorb high frequency spike energy.


Designing the low-side gate driver chip according to the above suggestions can greatly improve the reliability of the circuit operation. At the same time, considering the popularity of wide-bandgap switching devices such as SiC MOSFETs, in such applications, the driving voltage and switching frequency increase, and the power transistor is more sensitive to parasitic parameters. In order to cover this harsher application scenario and simplify the system design, TI’s new generation of low-side gate driver chip UCC27624 has been optimized for the above-mentioned risk points, which greatly improves the robustness of the chip:

1. The maximum withstand voltage of VDD up to 30V improves the safety margin;

2. The noise suppression capability of the internal LDO is improved, thereby improving the robustness of the chip in a noisy environment;

3. Input voltage withstand capability as low as -10V;

4. Wider output voltage pulse withstand capability, and -5A reverse pulse current withstand capability.


This paper analyzes the possible risks of the input, output and power supply stages of the low-side gate driver, and proposes corresponding optimization measures to improve the reliability of the system in increasingly severe operating conditions. In addition, this article describes the improvements made by TI’s next-generation gate driver, the UCC27624, to address these risks. Helps engineers design more robust systems.


How to overcome negative voltage transients on low-side gate drivers’ inputs

Source: TI, Author: Terry Liang

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