Realization of Ethernet Communication Based on Ethernet Controller NC28J60 and HR901170A

Prior to this, the optional standalone Ethernet controllers for embedded system development were designed for personal computer systems, such as RTL8019, AX88796L, DM9008, CS8900A, LAN91C11l, etc. These devices are not only complex in structure, bulky, and expensive. At present, most Ethernet controllers on the market have more than 80 pins, while the ENC28J60 conforming to the IEEE 802.3 protocol has only 28 pins, which can provide corresponding functions. , and can greatly simplify the related design and reduce the space.

Authors: Zhou Xiaoyang, Cheng Hong, Zhang Xiaoyuan

The NC28J60 is a 28-pin stand-alone Ethernet controller recently introduced by Microchip Technology.

Prior to this, the optional standalone Ethernet controllers for embedded system development were designed for personal computer systems, such as RTL8019, AX88796L, DM9008, CS8900A, LAN91C11l, etc. These devices are not only complex in structure, bulky, and expensive. At present, most Ethernet controllers on the market have more than 80 pins, while the ENC28J60 conforming to the IEEE 802.3 protocol has only 28 pins, which can provide corresponding functions. , and can greatly simplify the related design and reduce the space.

1 Structure and function

The ENC28J60 Ethernet controller using the industry standard Serial Peripheral Interface (SPI) has the following key features:

◆Comply with IEEE 802.3 protocol. Built-in lOMbps Ethernet physical layer device (PHY) and media access controller (MAC), which can reliably send and receive packet data according to industry-standard Ethernet protocols.

◆With programmable filtering function. Special filters, including Microchip’s programmable pattern-matching filters, can automatically evaluate, accept or reject Magic Packet, Unicast, Multicast or Broadcast packets to relieve the host microcontroller processing load.

◆lOMbps SPI interface. Industry-standard serial communication ports enable network connectivity for 8-bit microcontrollers as low as 18 pins.

◆ Programmable 8KB dual-port SRAM buffer. The storage, retrieval and modification of information packets are carried out in an efficient manner to reduce the memory load of the master microcontroller. The buffer memory provides a flexible and reliable data management mechanism.

2 Hardware Design

The hardware design of ENC28J60 needs to pay attention to the reset circuit, clock oscillator, oscillator start timer, clock output pin, transformer, terminal and other external devices, input/output level and so on. (Figure 1 for reference) 2.1 Reset circuit ENC28J60 has a power-on reset (Power-on Reset) function, the low level on the RESET pin makes ENC28J60 enter the reset mode; there is a weak pull-up resistor inside the RKSlET pin. The hardware connection of ENC28J60 is shown in Figure l.

Realization of Ethernet Communication Based on Ethernet Controller NC28J60 and HR901170A

2.2 Clock oscillator

ENC28J60 needs a 25MHz crystal oscillator, which is connected to OSCl and OSC2 pins; it can also be driven by an external clock signal. At this time, the external clock of 3.3V is connected to the OSCl pin, and OSC2 is disconnected or grounded through a resistor to reduce system noise.

2.3 Oscillator Startup Timer

The ENC28J60 has an oscillator start-up clock OST (Oscillator Start-upTimer), which is powered on for 7500 clock cycles (300μs). After the OST expires, the internal PHY can work normally. At this time, messages cannot be sent or received. The host computer can decide whether to set the sending or receiving message by detecting the state of the CLKRDY bit in the ESTAT register of ENC28J60.

It should be noted that when ENC28J60 is powered on reset or wakes up from Power-Down mode, it must check whether CLKRDY in the ESTAT register is set. Only after CLKRDY is set, messages can be sent and received, and related registers can be accessed.

2.4 Clock output pin

The CLKOUT pin provides the clock source for other devices in the system. The CLKOUT pin remains low after power-on, and the OST counts after reset. After the OST expires, CLKOUT outputs a clock with a frequency of 6.25MHz.

The clock output function is disabled, adjusted and enabled through the ECOCON register. The clock output can be set to divide by 1, 2, 3, 4, and 8, and the default is 4 after power-on. After the configuration of the ECOCON register is changed, the CLKOUT pin has a delay of 80 to 320ns (holds a low level), and then outputs a clock signal with a fixed frequency according to the setting.

A soft reset or a reset signal on the RESET pin does not affect the state of the ECOCON register. Power-Down mode also does not affect the output of the clock. When the clock output is disabled, the CLKOUT pin is held low.

2.5 Transformers, Terminations and Other External components

To implement the Ethernet interface ENC28J60, several standard external components are required: pulse transformer, bias resistor, energy storage capacitor and decoupling capacitor.

The differential input pin (TPIN+/TPTN-) requires a 1:1 ratio pulse transformer to realize 10BASE-T. Differential output pins (TPOUT+/TPOUT-) require a pulse transformer with a ratio of 1:1 and a center tap. The transformer needs to have 2kV or higher isolation capability, anti-static. For the detailed requirements of the transformer, please refer to Chapter 16 “Electrical Characteristics” of the chip manual. Each part needs to be grounded through two 50Ω resistors with an accuracy of 1% and a 0.01μF capacitor in series.

The author adopts the integrated Ethernet isolation transformer RJ45 socket HR901170A of Zhongshan Hanren Company.

The analog circuit inside ENC28J60 needs to connect a 2kΩ, 1% bias resistor between the RBIAS pin and the ground. Some digital circuits work at 2.5V to reduce power consumption; ENC28J60 integrates a 2.5V regulator to generate the required voltage, and a 10μF capacitor needs to be connected between the VCAP pin and the ground to ensure the stability of the power supply (The 2.5V regulator is not designed for external loads).

All power supply pins (VDD, VDDOSC, VDDPLL, VDDRX, VDDTX) must be connected to the same external 3.3V power supply; similarly, all grounds (VSS, VSSOSC, VSSPLL, VSSTX) must be connected to the same external on the ground. Each power supply pin and the ground should be connected to an O. Decoupling with a 1µF ceramic capacitor (as close as possible to the supply pins).

Driving the twisted pair interface requires a large current, so the power line should be as wide as possible, and the connection with the pin should be as short as possible to reduce the consumption of the internal resistance of the power line.

2.6 Input and output levels

The ENC28J60 is a 3.3 V CMOs device, but it is designed to be easily integrated into a 5 V system: the SPI, CS, SCK, SI inputs, like the RESET pin, are all 5V tolerant. A unidirectional level shifter may be required when the SPI and interrupt inputs are not compatible with the 3.3V driven CM0S output. 74HCT08 (four AND gates), 74ACTl25 (four tri-state buffers) and many 5VCMOS buffer chips with TTL level inputs can provide the required level shifting.

2.7 LED Configuration

The LEDA and LEDB pins support automatic polarity detection at reset. It can drive LEDs directly or sink current. The ENC28J60 detects the LED connection at reset and drives it according to the default setting of the PHLCON register. LED polarity transitions during operation cannot be detected by Yu until the next system reset. The connection of LEDB is rather special. It is detected during the reset process to determine how to initialize the PDPXMD bit of the PHCONl register. If LEDB drives the LED directly, the PHCON1.PDPXMD bit is cleared, and the PHY works in half-duplex mode; if LEDB absorbs reverse current to light the LED, then PHCON1. PDPXMD is set, PHY works in full-duplex mode; if LEDB is not connected, then PHCONl. PDPXME) the value after reset is undefined. The host controller must then set this bit appropriately to make the PHY work in the desired state (half-duplex or full-duplex).

3 software interface

3.1 SPI interface

The SPI interface (Serial Penpheral Interface) is a synchronous, full-duplex serial interface based on a master-slave configuration. It is a 4-wire interface – master-out/slave (MOSI). Master/Slave Out (MISO), Serial Clock (SCK), Slave Select (SSEL).

There can be multiple masters or slaves on the same bus, but only one master and one slave can communicate at the same time. In a data transmission process, the data is sent and received synchronously: the master sends 1 byte of data to the slave, and the slave also returns 1 byte of data to the master. Data transfer is in principle full duplex; in practice, however, in most cases only one direction of data flow contains meaningful data.

The main feature of the SPI format is the invalid state and phase of the SCK signal, and the clock for data transmission is provided by the host. Commonly used clock settings are based on two parameters, Clock Polarity (CPOL) and Clock Phase (CPHA). CP0L defines the active state of the SPI serial clock, while CPHA defines the clock phase relative to the slave output data bits. The settings of CPOL and CPHA determine the clock edge on which data is sampled.

Depending on the settings of CPOL and CPHA, there are 4 SPI modes, as listed in Table 1.

Realization of Ethernet Communication Based on Ethernet Controller NC28J60 and HR901170A

3.2 Connection between ENC28J60 and MCU

The connection of the ENC28J60 to the microcontroller MCU is achieved through SPI and supports 10 Mbps. For the chip without SPI interface, it can be realized by simulating the SPI interface with the I/O port. ENC28J60 only supports SPI mode O,O.

The microcontroller can send commands through the SPI interface, visit the register of ENC28J60 or read and write the receive/send buffer to complete related operations. Reset can also be implemented by software through the SPI interface, and software reset does not affect the state of the RESET pin.

ENC28J60 has two interrupt outputs, which are used for event interrupt trigger and LAN wake-up host respectively.

The CPU adopts LPC2138 to realize the read and write operations of the SPI port with macro definitions. SOSPDR is the SPI data register. This bidirectional register provides the data to be sent and received for the SPI. The data to be sent is provided by writing to this register, and the data received by the SPI can be read from this register. SOSPSR is the SPI status register. The SPI interface needs to be initialized before operating on it. The source code for reading/writing the SPI interface is given below.

Realization of Ethernet Communication Based on Ethernet Controller NC28J60 and HR901170A

You can also use the SSP of LPC2138 to connect ENC28J60, it needs to be set to SPI mode. It should be noted that the SSP has an 8-frame receive/transmit FIFO, which will cause read/write errors if not handled properly. Because the existence of the buffer may break the timing of reading/writing ENC28J60.

4 Conclusion

Ethernet communication is realized on LPC2138+ENC28J60+HR901170A platform. Compared to other solutions, the system is extremely streamlined. For single-chip microcomputers without an open bus, although it is possible to connect other Ethernet controllers by simulating a parallel bus, in terms of efficiency and performance, it is better to use the SPI interface or the general I/O port to simulate the SPI interface to connect the ENC28J160. .

It can be seen that ENC28J60 is a unique independent Ethernet controller: the SPI interface enables small microcontrollers to have network connection functions; the integrated MAC and PHY do not require other peripherals; it has programmable filtering functions, which can automatically evaluate, receive or reject A variety of information packets are received, which reduces the processing load of the main control microcontroller; the internal programmable 8KB dual-port SRAM buffer is inherited, and the operation is flexible and convenient. The downside is that only 10BASE-T is supported.

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