Practical Challenges and Considerations of Filter Design for Precision ADCs

This article discusses the design challenges and considerations involved in implementing analog and digital filters in the ADC signal chain for optimal performance. As shown in Figure 1, the data acquisition signal chain can use analog or digital filtering techniques, or a combination of the two. Precision SAR and sigma-delta ADCs typically sample in the first Nyquist zone, so this article will focus on low-pass filters. The intent of this article is not to discuss specific design techniques for low-pass filters, but to discuss their application in ADC circuits.

Author: Steven Xie

Introduction

Precision analog-to-digital converters are used in a wide variety of applications, such as instrumentation and measurement, power line protection, process control, motor control, and more. At present, the resolution of SAR ADC can reach 18 bits or even higher, and the sampling rate is several MSPS; the resolution of Σ-Δ ADC can reach 24 bits or even 32 bits, and the sampling rate is hundreds of kSPS. In order to take full advantage of high-performance ADCs without limiting their capabilities, users face increasing difficulties in reducing noise in the signal chain, such as implementing filters.

This article discusses the design challenges and considerations involved in implementing analog and digital filters in the ADC signal chain for optimal performance. As shown in Figure 1, the data acquisition signal chain can use analog or digital filtering techniques, or a combination of the two. Precision SAR and sigma-delta ADCs typically sample in the first Nyquist zone, so this article will focus on low-pass filters. The intent of this article is not to discuss specific design techniques for low-pass filters, but to discuss their application in ADC circuits.

Practical Challenges and Considerations of Filter Design for Precision ADCs
Figure 1. General Data Acquisition Signal Chain

Ideal and practical filters

An ideal low-pass filter should have a very steep transition band, and its passband should have excellent gain flatness, as shown by the dashed brick wall in Figure 2. Additionally, stopband attenuation should reduce any residual out-of-band signal to zero. The responses of some common practical filters are shown as colored lines in Figure 2. This response can affect the fundamental signal if the passband gain is not flat or rippled. The stopband attenuation is not infinite and limits the screening of out-of-band noise. The transition band may also not have a steep roll-off, resulting in poor attenuation of noise around the cutoff frequency. Also, all non-ideal filters introduce phase or group delay.

Practical Challenges and Considerations of Filter Design for Precision ADCs
Figure 2. Amplitude response comparison of ideal and practical filters

Analog Filters vs Digital Filters

An analog low-pass filter removes high-frequency noise and interference from the signal path prior to ADC conversion, helping to avoid aliasing noise contaminating the signal. It also eliminates the effects of overdrive signals outside the filter bandwidth and avoids modulator saturation. In the event of input overvoltage, the analog filter also limits the input current and attenuates the input voltage. Therefore, it can protect the ADC input circuit. Noise spikes superimposed on a near-full-scale signal can saturate the ADC’s analog modulator, which must be attenuated with an analog filter.

Since digital filtering occurs after conversion, noise injected during conversion can be removed. In practice, the sampling rate is much higher than twice the fundamental signal frequency indicated by Nyquist theory. Therefore, post-digital filters can utilize filtering techniques for higher signal-to-noise ratios and higher resolutions to reduce noise injected during conversion, such as input noise outside the signal bandwidth, power supply noise, reference noise, digital Interface feedthrough noise, ADC chip thermal noise, or quantization noise.

Table 1 briefly lists the advantages and disadvantages of analog filters versus digital filters.

Table 1. Analog Filters vs. Digital Filters

analog filter

digital filter

Design complexity

High (for high performance filters)

Low

cost

High (depending on selected analog components)

low (available CPU time)

Delay

Low

high

additive noise

Increase in-band component thermal noise

Quantization may introduce digital noise

ADC input protection

Yes

no

programmable

no

Yes

Drift error

Yes

no

aging

Yes

no

Multi-channel matching error

Yes

no

Analog Filter Considerations

Anti-aliasing filters are placed before the ADC, so these filters must be analog filters. An ideal antialiasing filter has the following properties: unity gain in the passband, no gain variation, and aliasing attenuation levels consistent with the theoretical dynamic range of the data conversion system used.

Depending on the architecture, the ADC will have different input resistances, which can affect the input filter design. The following considerations relate to the design of the ADC analog input filter.

Limitations of RC Antialiasing Filters Interfacing with ADC Front Ends

An example of an RC filter application for the AD7980ADC is shown in Figure 3 in Alan Walsh’s article “Front-End and Amplifier and RC Filter Design for Precision SAR-Type Analog-to-Digital Converters” for Analog Dialogue magazine.

The calculated RC filter is a low pass filter with a cutoff bandwidth of 3.11 MHz. However, some designers may realize that 3.11 MHz is much greater than the input signal frequency of 100 kHz, so this filter is not effective in reducing out-of-band noise. For higher dynamic range, a 590 Ω resistor can be used instead for a C3 dB bandwidth of 100 kHz. There are two main problems with this approach. Since there is more attenuation in the passband, for the AD7980 ADC example, the amplitude attenuation around 100 kHz is up to 30%, so the signal chain accuracy is greatly reduced. The smaller the bandwidth, the longer the settling time, which prevents the AD7980’s internal sample-and-hold capacitor from charging within the specified acquisition time for the next valid conversion. This results in reduced ADC conversion accuracy.

The designer should ensure that the RC filter before the ADC fully settles within the target acquisition time. This is especially important for precision ADCs that require larger input currents or have equivalently smaller input impedances. Some sigma-delta ADCs require the highest input RC value in unbuffered input mode. An ultra-narrow low-pass filter with a larger resistance or capacitance can be placed before the input amplifier, which typically has a larger input impedance. Alternatively, an ADC with very high input impedance can be selected, such as the ADAS3022 which has an input impedance of 500 MΩ.

Practical Challenges and Considerations of Filter Design for Precision ADCs
Figure 3. RC Filter Using AD7980, 16-Bit, 1 MSPS ADC

1. Filter Settling Time for Multiplexed Sampling Signal Chains

Multiplexed input signals often contain large steps when switching between channels. In the worst case, one channel is at negative full scale and the next channel is at positive full scale (see Figure 4). In this case, when the multiplexer switches channels, the input step size will be the full scale of the ADC.

For these channels, a single-channel filter can be used after the multiplexer, making the design simpler and less expensive. As mentioned above, analog filters necessarily introduce settling time. Each time the multiplexer switches between channels, the single-channel filter must be charged to the value of the selected channel, thus limiting the throughput rate. To increase throughput, it is possible to add a filter to each channel before the multiplexer, but doing so increases the cost.

Practical Challenges and Considerations of Filter Design for Precision ADCs
Figure 4. Multiplexed Input Signal Chain

2. Passband Flatness and Transition Band Limit vs Noise

Applications that experience high noise, especially those near the edge of the first Nyquist zone, require a filter with severe roll-off. However, it is known from practical analog low-pass filters: from low to high frequencies, the amplitude rolls off and there is a transition band. Increasing the filter stage or order improves the flatness of the in-band signal and narrows the transition band. However, the design of these filters is complex because they are so sensitive to gain matching that attenuation magnitudes of several orders cannot be achieved. Additionally, adding any element to the signal chain, such as a resistor or amplifier, introduces in-band noise.

Practical Challenges and Considerations of Filter Design for Precision ADCs
Figure 5. Ideal Butterworth filter transition bands of different orders

For some specific applications, the complexity and performance of the analog filter design requires trade-offs. For example, in a power line relay protection application using the AD7606, the protection channel is less accurate than the measurement channel for a 50 Hz/60 Hz fundamental input signal and its associated first five harmonics. The guard channel can use a first-order RC filter, while the measurement channel uses a second-order RC filter to provide better in-band flatness and sharper roll-off transitions.

3. Phase Delay and Matching Error of Simultaneous Sampling

Filter design is not only about frequency design, users may also need to consider the time domain characteristics and phase response of analog filters. In some real-time applications, phase delay can be very important. If the phase varies with the input frequency, the phase variation will be even worse. The phase change of the filter is generally measured by the group delay. With non-constant group delay, the signal spreads out in time, resulting in a poor impulse response.

For multi-channel simultaneous sampling applications, such as phase current measurement in motor control or power line monitoring, phase delay matching errors should also be considered. Make sure that the additional phase delay matching error introduced by the filter on multiple channels is negligible or within the signal chain error budget for the operating temperature range.

4. Component selection challenges for low distortion and low noise applications

For low harmonic distortion and low noise applications, the user must select the correct components for the signal chain design. Analog electronics are not perfectly linear and can cause harmonic distortion. Walsh’s article discusses how to choose a low-distortion amplifier and how to calculate amplifier noise. Active components such as amplifiers require low THD+N, while also taking into account the distortion and noise of passive components such as common resistors and capacitors.

There are two sources of nonlinearity in resistance: the voltage coefficient and the power coefficient. Depending on the application, high-performance signal chains may require the use of resistors fabricated with specific technologies, such as thin-film or metal resistors. If not chosen properly, the input filter capacitors can cause significant distortion. If the budget allows, polystyrene and NP0/C0G ceramic capacitors are good candidates to improve THD.

In addition to amplifier noise, resistors and capacitors also have Electronic noise, the latter resulting from thermal perturbations of charge carriers inside an electrical conductor in equilibrium. The thermal noise of the RC circuit has a simple expression, the resistance R is required to meet the filtering requirements, and the higher the R, the greater the corresponding thermal noise. The noise bandwidth of an RC circuit is 1/(4RC).

In addition to amplifier noise, resistors and capacitors also have electronic noise, the latter resulting from thermal perturbations of charge carriers inside an electrical conductor in equilibrium. The thermal noise of the RC circuit has a simple expression, the resistance R is required to meet the filtering requirements, and the higher the R, the greater the corresponding thermal noise. The noise bandwidth of an RC circuit is 1/(4RC).

Practical Challenges and Considerations of Filter Design for Precision ADCs

kB (Boltzmann constant) = 1.38065 × 10C23m2kgsC2KC1
T is the temperature (K)
f is the approximate bandwidth of the brick wall filter

Figure 6 shows the effect of NP0 and X7R capacitors on THD performance on the EVAL-AD7960FMCZ evaluation board: (a) shows the spectrum of a 10 kHz sine wave tone, C76 and C77 are 1 nF 0603 NP0 capacitors, and (b) Shows the spectrum when using a 1 nF 0603 X7R capacitor.

Practical Challenges and Considerations of Filter Design for Precision ADCs
(a) 0603 1nF NP0 capacitor
Practical Challenges and Considerations of Filter Design for Precision ADCs
(b) 0603 1nF X7R Capacitor
Figure 6. Effect of NP0 and X7R Capacitors on THD on the EVAL-AD7960FMCZ Evaluation Board

With the preceding design considerations in mind, an active analog filter can be designed using Analog Devices’ Analog Filter Wizard. It calculates capacitor and resistor values ​​based on application requirements and selects the appropriate amplifier.

Digital Filter Considerations

SAR and Σ-Δ ADCs are steadily achieving higher sampling rates and input bandwidths. Oversampling a signal at twice the Nyquist rate spreads the ADC quantization noise energy evenly over twice the frequency band. This makes it easy to design digital filters to limit the frequency band of the digitized signal and then decimate to provide the desired final sample rate. This technique reduces in-band quantization error and improves ADC SNR. It also relaxes the filter roll-off requirements, thereby reducing the stress on the anti-aliasing filter. Oversampling reduces filter requirements, but requires higher sampling rate ADCs and faster digital processing.

1. The actual SNR improvement achieved by using an oversampling rate for the ADC

The SNR improvement achieved with oversampling and decimation filters can be found from the theoretical SNR of an N-bit ADC: SNR = 6.02 × N + 1.76 dB + 10 × log10[OSR]OSR = fs/(2 × BW). Note: This formula only applies to ideal ADCs with only quantization noise.

Practical Challenges and Considerations of Filter Design for Precision ADCs
Figure 7. Nyquist Converter Oversampling

There are many other factors that can introduce noise into the ADC conversion code. Examples include signal source and signal chain device noise, chip thermal noise, shot noise, power supply noise, reference voltage noise, digital feedthrough noise, and phase noise due to sampling clock jitter. This noise may be evenly distributed in the signal frequency band and appear as flicker noise. Therefore, the actual ADC SNR improvement achieved is generally lower than the calculated value.

2. Dynamic improvement with oversampling on the EVAL-AD7960FMCZ evaluation board

In application note AN-1279, the measured dynamic range of the 18-bit AD7960 ADC at 256× oversampling is 123 dB. This is used in high performance data acquisition signal chains such as spectral analysis, magnetic resonance imaging (MRI), gas chromatography, vibration, oil/gas exploration and seismic systems.

As shown in Figure 8, the measured oversampling dynamic range is 1 dB to 2 dB lower than the theoretical SNR improvement calculation. The reason is that the low frequency noise from the signal chain components limits the overall dynamic range performance.

Practical Challenges and Considerations of Filter Design for Precision ADCs
(a) Dynamic range without OSR
Practical Challenges and Considerations of Filter Design for Precision ADCs
(b) Dynamic range with OSR = 256
Figure 8. Dynamic range improvement at OSR 256

3. Take advantage of integrated digital filters in SAR and sigma-delta ADCs

Digital filters are usually located in FPGAs, DSPs or processors. To reduce system design effort, Analog Devices offers several precision ADCs with integrated post-digital filters. For example, the AD7606 integrates a first-order post-digital sinc filter for oversampling. It is easy to configure, just pull up or pull down the OS pin. The AD7175-x sigma-delta ADCs have not only traditional sinc3 filters, but also sinc5 + sinc1 and enhanced 50 Hz/60 Hz rejection filters. The AD7124-x provides fast settling mode (sinc4 + sinc1 or sinc3 + sinc1 filter) capability.

4. Delay tradeoffs for multiplexed sampling ADCs

Delay is a disadvantage of digital filters, and it depends on the digital filter order and master clock rate. For real-time applications and loop response times, delays should be limited. The output data rate listed in the data sheet refers to the rate at which conversion results are valid when continuous conversions are performed on a single channel. When the user switches to another channel, it takes some extra time to set up the sigma-delta modulator and digital filter. The settling time associated with these converters is the time it takes for the output data to reflect the input voltage after a channel change. After a channel change, to accurately reflect the analog input, the digital filter must be cleared of all data associated with the previous analog input.

Previously, the channel switching speed of sigma-delta ADCs was much slower than the data output rate. Therefore, in switching applications such as multiplexed data acquisition systems, it must be understood that conversion results are obtained at a rate several times lower than that achievable when sampling a single channel continuously.

Some of ADI’s new sigma-delta ADCs, such as the AD7175-x, have built-in digital filters optimized to reduce settling time when switching channels. The AD7175-x’s sinc5 + sinc1 filters are primarily intended for multiplexing applications and allow single-cycle settling at output data rates of 10 kSPS and lower.

5. Digital filters avoid aliasing by decimation

As discussed in many articles, the higher the oversampling frequency, the easier the analog filter design is. When the sampling rate is higher than that required to meet the Nyquist criterion, simpler analog filters can be used to avoid aliasing at very high frequencies. It is difficult to design an analog filter that can attenuate the desired frequency band without distortion, but it is easy to design an analog filter that utilizes oversampling to suppress higher frequencies. This makes it easy to design digital filters to limit the frequency band of the converted signal, and then decimate to provide the desired final sample rate without losing the desired information.

Before implementing decimation, you need to ensure that this resampling does not introduce new aliasing problems. After decimation, ensure that the input signal conforms to Nyquist’s theory for sampling rate.

The EVAL-AD7606/EVAL-AD7607/EVAL-AD7608EDZ evaluation boards can operate at 200 kSPS per channel. In the test below, it is configured with a sampling rate of 6.25 kSPS and an oversampling ratio of 32. Then, a 3.5 kHz C6 dBFS sine wave is applied to the AD7606. Figure 9 shows a C10 dBFS aliased image at 2.75 kHz (6.25 kHz C 3.5 kHz). Therefore, if there is no qualified anti-aliasing analog filter before the ADC, when oversampling is used, the digital filter may cause aliasing images due to decimation. An analog antialiasing filter should be used to remove such noise spikes superimposed on the analog signal.

Practical Challenges and Considerations of Filter Design for Precision ADCs
Figure 9. Aliasing at OSR Decimation Rate Less than Nyquist Frequency

in conclusion

The challenges and considerations discussed in this article can help designers design practical filters to achieve the goals of precision acquisition systems. The analog filter must interface with the non-ideal input structure of the SAR or sigma-delta ADC without violating the system error budget, and the digital filter should not introduce errors on the processor side. This is no simple task, and trade-offs must be made in terms of system specifications, response time, cost, design effort, and resources.

Reference circuit

Holdaway, Mark. “Antialiasing Filter Design for ADCs.” EDN, 2006.
Walsh, Alan. Front-end amplifier and RC filter design for precision SAR-type analog-to-digital converters. Analog Dialogue, Vol. 46, No. 4, 2012.
Wescott, Tim; Wescott Design Services. “Sampling: What Nyquist Didn’t Say and What to Do”. Wescott Symposium, 2015.
Butterworth filter design.
Analog and digital anti-aliasing filtering.

author

Practical Challenges and Considerations of Filter Design for Precision ADCs

Steven Xie

Steven Xie joined ADI Beijing in 2011 and is an ADC applications engineer at the China Design Center. He is responsible for the technical support of SAR ADC products in the Chinese market. Before that, he was a hardware designer on the Ericsson CDMA team for four years. In 2007, Steven graduated from Beihang University with a master’s degree in Communication and Information Systems.

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