Output Characteristics and Application Design of Linear Power MOSFETS

Applications such as Electronic loads, linear regulators or class A amplifiers operate within the linear region of power MOSFETs, which requires high power dissipation capability and extended forward bias safe operating area (FBSOA) characteristics. This mode of operation differs from the usual way of using power MOSFETs, which act like an “on-off switch” in switch-mode applications. In linear mode, power MOSFETs are subject to high thermal stress due to high drain voltage and current occurring simultaneously, resulting in high power dissipation.When the thermoelectric stress exceeds a certain critical limit, thermal hot spots develop in the silicon, leading to device failure[1].

Applications such as electronic loads, linear regulators or class A amplifiers operate within the linear region of power MOSFETs, which requires high power dissipation capability and extended forward bias safe operating area (FBSOA) characteristics. This mode of operation differs from the usual way of using power MOSFETs, which act like an “on-off switch” in switch-mode applications. In linear mode, power MOSFETs are subject to high thermal stress due to high drain voltage and current occurring simultaneously, resulting in high power dissipation.When the thermoelectric stress exceeds a certain critical limit, thermal hot spots develop in the silicon, leading to device failure[1].

Output Characteristics and Application Design of Linear Power MOSFETS
Figure 1 Output characteristics of N-channel power MOSFET

Figure 1 shows the typical output characteristics of an N-channel power MOSFET, which depicts the different modes of operation. In the cut-off region, the gate-source voltage (VGS) is less than the gate-threshold voltage (VGS(th)) and the device is in an open or off state. In the ohmic region, the device acts as a resistor with an almost constant resistance RDS(on) equal to Vds/Ids. In linear mode of operation, the device operates in the “current saturation” region where the drain current (Ids) is a function of the gate-source voltage (Vgs) and is defined by:

Output Characteristics and Application Design of Linear Power MOSFETS

where K is a temperature and device geometry dependent parameter and gfs is the current gain or transconductance. As the drain voltage (VDS) increases, the positive drain potential opposes the gate voltage bias and reduces the surface potential in the channel. The charge of the channel inversion layer decreases as Vds increases and eventually, when the drain voltage is equal to (Vgs C Vgs(th)), the charge becomes zero.This point is called the “channel pinch point”, at which point the drain current becomes saturated[2].

FBSOA is the data sheet figure of merit, which defines the maximum allowable operating point. Figure 2 shows the typical FBSOA characteristics of an N-channel power MOSFET. It is limited by the maximum drain-to-source voltage VDSS, the maximum conduction current IDM and the constant power dissipation line for different pulse durations. In this figure, this set of curves shows a DC line and 4 single-pulse operating lines, 10ms, 1ms, 100us and 25us, respectively. The top of each line is truncated to limit the maximum drain current and is bounded by a positive slope line defined by the Rds(on) of the device. The right side of each line terminates at the rated drain-source voltage limit (Vdss). Each line has a negative slope and is determined by the maximum allowable power dissipation of the device Pd:

Output Characteristics and Application Design of Linear Power MOSFETS

where ZthJC is the transient terminal impedance from junction to case and TJ(max) is the maximum allowable junction temperature of the MOSFET.

Output Characteristics and Application Design of Linear Power MOSFETS
Figure 2 Typical FBSOA diagram of N-channel power MOSFET

These theoretically constant power curves are derived from calculations assuming a substantially uniform junction temperature across the power MOSFET die. This assumption is not always true, especially for large die MOSFETs. First, the edge of a MOSFET die soldered to a power package mount is typically cooler than the center of the die as a result of lateral heat flow. Second, material defects (die attach voids, thermal grease cavities, etc.) may lead to a local decrease in thermal conductivity, i.e. a local temperature increase. Third, fluctuations in dopant concentration, gate oxide thickness and fixed charge will cause fluctuations in the local threshold voltage and current gain (gfs) of the MOSFET cells, which will also affect the local temperature of the chip. Mold temperature changes are virtually harmless when operating in switch mode. However, they can trigger catastrophic failures in linear mode operation with pulses lasting longer than the time required for heat transfer from the junction to the heat sink. Modern power MOSFETs optimized for switch-mode applications were found to have limited ability to operate in the lower right corner of the FBSOA diagram (the region to the right of the electrothermal instability boundary in Figure 2).

Electrothermal instability (ETI) can be understood as the result of a positive feedback mechanism on the surface of the power MOSFET that forces a linear operating mode:

Local rise in junction temperature
This results in a local reduction in Vgs(th) (the temperature coefficient of the MOSFET threshold voltage is negative)
This results in an increase in the local current density Jds`(Vgs C Vgs(th))2
The increase in local current density leads to an increase in local power dissipation and a further increase in local temperature.

Depending on the duration of the power pulse, heat transfer conditions, and characteristics of the MOSFET cell design, ETI can cause all of the MOSFET current to concentrate into the current filament and form a “hot spot”. This typically causes the MOSFET cells in the designated area to lose gate control and turn on parasitic BJTs, damaging the device.

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