Jiang Shangyi’s appearance at the China Chip Creation Annual Conference: Moore’s Law is approaching the physical limit

IT House January 16 news According to the “Science and Technology Innovation Board Daily”, the 2nd China SMIC Annual Meeting was held today. Jiang Shangyi, vice chairman of SMIC, appeared and answered questions such as SMIC’s development direction. IT House learned that this is Jiang Shangyi’s first appearance after joining SMIC.

Jiang Shangyi said:

The progress of Moore’s Law is approaching the physical limit, and the current ecological environment is no longer applicable

Advanced technology will definitely go on, and advanced packaging is a technology laid out for the post-Moore era. SMIC will develop in both advanced technology and advanced packaging.

The development of packaging and circuit board technology is relatively backward, gradually becoming the bottleneck of system performance

State-of-the-art silicon processes are only available for a very small number of products in high demand

With the advent of the last smart phone era, the requirements for chips are different. There are many kinds of chips, and the changes are fast, but the amount is not necessarily large.

The chip supply chain has ushered in a reorganization. Different applications require different chips, and the demand for chips has become diversified.

The semiconductor application market has changed from the main chips in the hands of a few suppliers to the main chips no longer in the hands of a few manufacturers

The development trend in the post-Moore era is to develop advanced packaging and circuit board technology, that is, integrated chips, which can make the tightness of the connection between the chips and the overall system performance similar to that of a single chip.

Our semiconductor industry needs to establish a complete ecological environment to win in the global market competition, including equipment + raw materials → silicon wafer process → packaging and testing → chip products → system products, as well as EDA Tools, Standard Cells, IP’s, Testing, Inspect i on In order to achieve the optimization of system performance.

In addition, Wu Hanming, academician of the Chinese Academy of Engineering and dean of the School of Micro-Nano Electronics of Zhejiang University, also attended and delivered a speech. He said that there are three major challenges in the chip manufacturing process. Among them, the basic challenge is precision graphics, the core challenge is new materials and new processes, and the ultimate challenge is Improve yield.

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