Since the invention of the transistor, integrated circuits have been developing in accordance with Moore’s Law-every 18 months, the feature size of the transistor is reduced by half, the size is reduced, higher density integration is achieved, the function, performance, and energy efficiency ratio are greatly improved, and the cost is reduced. Micro-processors and semiconductor memory chips have shown the same development characteristics in the past half a century.
In order to continue to shrink the feature size, as the most core process for realizing the pattern line width-lithography technology, from the original ultraviolet light G-line line (436nm) to today’s extreme ultraviolet EUV (13.5nm) lithography technology. MOSFET transistors have also entered 3D FINFET from the early two-dimensional structure to continue Moore’s Law. This year, the HiSilicon Kirin 9000 series is manufactured using a 5nm process node, and a single chip contains approximately 15 billion transistors.
At present, leading international manufacturers such as TSMC, Samsung, and Intel are still actively engaged in research and development dedicated to continuously reducing the feature size of transistors. This year, TSMC’s annual technology seminar discussed the use of extreme ultraviolet EUV lithography to shrink the process node to 3nm. South Korea’s Samsung Electronics announced its next-generation 3nm node plan and schedule. The United States IBM also released a 2nm device R&D plan.
However, the initial CMOS process node corresponds to the gate length of the transistor, which intuitively reflects the degree of miniaturization of integrated circuit transistor devices. As Intel CEO Pat Gelsinger pointed out at the Intel Accelerated conference recently, the diversification of solutions after entering the era of 3D transistors no longer refers to any specific measurement methods, and cannot fully demonstrate how to achieve the best balance of performance and performance. It is also said that Moore’s Law is essentially an economic law. According to its guidelines, everyone is profitable and profitable. This was true in the early stages of integrated circuit development, and it lasted for more than half a century. However, after entering the 1Xnm node, tens of billions of dollars have been invested in a wafer line at every turn. Therefore, how to achieve the balance of efficiency and performance has become the development strategy of the industry’s leading companies.
Leading companies accelerate the layout of 3D integrated packaging technology
With the advent of the post-Moore era, advanced integrated packaging technology has been pushed to the center of the stage. Recently, leading semiconductor manufacturers such as TSMC, Intel, and Samsung are accelerating the deployment of 3D integrated packaging technology.
Recently, Yang Rui, research director of the Taiwan Institute of Industrial Technology, predicted that TSMC will dominate the chip manufacturing industry for another five years, and 3D integrated packaging is the key. If Moore’s Law is to pack more transistors into a chip by reducing the feature line width to achieve more functions, then the advanced integrated packaging in the post-Moore era is to stack more bare chips like a stacked bed frame house. Together and tucked into one package. Moreover, the bare chips stacked in the horizontal and vertical directions are interconnected by the smallest-sized conductive channels.
Among them, the channel that realizes the electrical connection in the thickness direction of the bare chip is through-silicon via technology (Through-Si-Via, TSV), and the electrical connection between stacked bare chips is the micro-bump, etc., on the same horizontal plane The electrical connection channel between the bare chips is the Redistribution Layer (RDL). These three are the key elements of advanced integrated packaging in the post-Moore era.
Currently, the most representative postmolar advanced integrated packaging technologies include CoWoS (Chip-on-Wafer-on-Substrate), 3D SoIC (System-on-Integrated-Chips), and InFO_SoW (Integrated Fan-outWafer-Level) launched by TSMC. -Package_System-on-Wafer) and so on. Today’s Fujitsu A64FX processor, which is ranked first in the world’s TOP 500 supercomputer list, uses TSMC’s CoWoS packaging technology. my country’s Huawei HiScend 910 and Suiyuan Smart Technology DTU1.0 and other chips are also reported to use TSMC’s CoWoS technology, and the recently reported Tesla Dojo training chip also uses TSMC’s InFO-SOW technology platform.
Postmolar advanced integrated packaging technology also includes 2.5D embedded multi-interconnect bridge (EMIB) technology introduced by Intel, 3D packaging Foveros technology, and Co-EMIB technology that combines EMIB and Foveros. In 2020, they launched Lakefield Micro The processor uses 3D packaging Foveros technology. Recently, South Korea’s Samsung Electronics also announced its 3D packaging technology as Extended-Cube, or X-Cube for short. The SRAM layer can be stacked on the logic layer through TSV interconnection, and the separation of SRAM and logic part can free up more space for stacking. With more memory, this technology can already be used in 7nm and even 5nm processes.
In the post-Moore era, a variety of advanced packaging technologies and advanced process nodes have a clear trend of integration
It can be said that the pursuit of advanced integrated packaging has been accompanied by the development of the integrated circuit industry, which at the same time stems from the exploration of the pursuit of the limit of transistor integration and the concerns about the prospect of failure of Moore’s Law. As early as 1976, researchers from General Electric Company of the United States proposed to develop conductive channels that can penetrate through the thickness of the IC chip body to support the stacking and integration of the chip body. However, at that time, integrated circuits were in their youth and were unable to compete with Moore’s Law, the technology route that continues to shrink the size of transistors. Around 2002, integrated circuits entered the deep sub-micron node, and the Japanese semiconductor industry launched a super semiconductor chip research and development program, with a view to developing a technology for stacking and integrating bare chips to achieve higher-density 3D integration. Around 2007, South Korea’s Samsung Electronics demonstrated the multi-layer bare chip stacking integration based on TSV interconnection, once again pushing the development of advanced integrated packaging technology for integrated circuits to a climax. It was also during this period that my country also launched a research plan on TSV three-dimensional packaging technology. However, the A10 processor launched by Apple in 2016 adopted TSMC’s InFO advanced packaging technology, and Intel adopted EBIM technology to apply its programmable logic device products. The social popularity of advanced integrated packaging technology represented by TSV interconnect technology linear decrease.
With the rapid development of artificial intelligence, big data, cloud computing, heterogeneous computing, etc., the Chiplet design concept has re-emerged. In fact, Chiplet is not a new concept. It uses advanced integrated packaging technology to mix and integrate bare chips of different process nodes to solve the problems of yield, cost, development cost, and long cycle time of a large-area single SoC chip brought about by the continuation of traditional Moore’s Law. , Especially in the case of high value but insufficient product market demand, the IP reuse brought by Ciplet will bring more benefits.
Today, the post-Moore advanced integrated packaging technology with TSV interconnect, RDL, and Micro-bump as the core elements presents the characteristics and trends of fusion with Chiplet and Moore’s law cutting-edge process nodes, and has become a SoC chip that supports high-performance computing. The most advanced technology platform is a key point in the strategic layout of technology development for leading companies such as TSMC, Intel, and Samsung Electronics.
The post-Moore era advanced packaging and Chiplet’s design concepts are mutually supportive
When the interconnect size between the bare chips is close to the interconnect size of the transistors in the chip, is the bare chip body of the post-Moore stacked bed frame a chip or a package? It can be said that the package is not only a chip, but also a system.
In the future, the feature size of key interconnection elements such as TSV interconnection, RDL, and Micro-bump will be further reduced, with more types and numbers of chips, and more stacked layers, standardization of architecture and interfaces, and expansion of the penetration and application of multi-signal domain and multi-category devices. It will be an important development direction of advanced integrated packaging in the post-Moore era.
Although the concept of advanced integrated packaging in the post-Moore era is simple and easy to understand, engineering implementation is very challenging. From the process level, the introduction of TSV interconnection process and the addition of ultra-thin wafer operations and other process steps will seriously affect the process of integrated circuit chips, compatibility, manufacturability, process monitoring and control, etc. A series of challenges, which require industry collaborations such as technology, materials, and equipment. From a design perspective, advanced packaging in the post-Moore era means that chip design has moved from traditional two-dimensional graphic design to three-dimensional space design, and must be supported by design methodology, EDA tools, three-dimensional architecture, and interface standardization.
The advanced integrated packaging in the post-Moore era is reshaping the supply chain and value chain of products, and is also affecting the industrial form and competitive landscape. Traditional IC products generally adopt the mode of division of labor and relay completion by IC foundries and packaging plants. Today, the balance of value is tilting toward foundries. Take Intel Lakefield microprocessor as an example. The TSV process and Chip-on-Wafer of integrated circuit chips are all completed by Intel. These links have become the most critical part of the technology chain, accounting for a relatively large product cost and adding value high. Moreover, the advantages of preconceptions are prominent. Once the ecology is formed, for latecomers, it means that the threshold is high and the market entry is more difficult.
The advanced packaging technology of the post-Moore era and Chiplet’s design philosophy support each other and achieve each other. In the manufacturing field, traditional packaging factories and uninvolved foundries may be in a disadvantageous competitive position. High-efficiency computing SoC chip design factories face The supply chain is concentrated, and there are fewer and fewer optional manufacturing plants, which are in a disadvantageous competitive position. However, it is also possible to open a window in the field of IC design and provide development opportunities for many small and medium-sized enterprises that focus on making special IC chips. What is the development prospect of Chiplet, especially whether the independent third-party Chiplet supplier’s business model is established, and who will benefit from it remains to be seen.
Around 2008, my country’s integrated circuit industry began to deploy advanced packaging technology in the post-Moore era. The project member units include well-known domestic universities and well-known domestic foundries and packaging companies. The start is not too late, and a series of research results have been obtained, and many have been cultivated. Advanced packaging materials and excellent equipment companies have made breakthroughs in the fields of CMOS image sensors, RF MEMS and other products. However, in view of the development of my country’s industrial chain such as high-performance computing CPUs, the industrial application of this field has lagged behind international leading companies such as TSMC and Intel, the gap is widening, and the technical threshold is raising. At present, advanced packaging technology is in a critical period of development. It is recommended that the national competent department strengthen top-level design and guidance, industry leading enterprises should play their responsibilities, the industry chain coordinated research, bravely climb the technological peak, solve the “stuck neck” problem, and lead the integrated circuit industry Safe and healthy development.
Author Ma Shenglin, Associate Professor, Department of Mechanical and Electrical Engineering, Xiamen University