[Guide]With the growth of server systems, the number and complexity of input/output (I/O) cards that contain control circuits to monitor servers have also increased year-on-year. The zero downtime system requires the user to insert the I/O card into the powered backplane. Although many IC suppliers have developed chips that can safely hot swap (Hot SwapTM) power and ground, so far, none of them can implement system data (SDA) and system clock ( SCL) line “hot-swappable” single-chip solution.
Since the SDA and SCL capacitors of each I/O card are directly added to the backplanes of these systems, the expansion of the system makes it difficult to meet the rise and fall time indicators. The LTC4300-1 allows users to insert the I/O card into a charged backplane without disrupting the data conversion of the backplane. It also provides two-way buffering and isolates the backplane and the capacitors on the card.
Figure 1 shows an application of LTC4300-1 safe hot-swappable SDA and SCL lines. The LTC4300 is located on the edge of the peripheral card, the ScLOUT pin is connected to the SCL bus of the card, and the SDAOUT pin is connected to the SDA bus of the card. When the card is inserted into the live backplane through the long and short pin connector, the ground is connected first, and then the VCC is connected.
Figure 1: Using LTC4300-1 hot-swappable SDA and SCL lines
After VCC is connected to ground, SDAIN and SCLIN are connected to the SDA and SCL lines on the backplane. At this time, the pre-charge circuit with a voltage of 1V works and forces the IV voltage to pass through the 100k nominal resistance to the low capacitance (less than 10pF) SDA and SCL pins, minimizing the worst voltage difference seen during connection. The pre-charge and low-capacitance characteristics minimize the interference of the backplane SDA and SCL buses during hot swapping.
During card insertion, the voltage on the SDA backplane bus and LTC4300-1 SDAIN pins is shown in Figure 2. The grounded 100pF capacitor tries to catch up with the capacitance equivalent to the SDA bus. Just before inserting, the SDAIN pin of LTC4300-1 is precharged to 1V, and the SDA bus backplane voltage is close to 4V. Due to the high impedance and low capacitance of the SDAIN pin, the voltage on the pin rises to the backplane voltage when it is inserted, so the backplane voltage is hardly affected. At this time, the two signals are shorted together.
Figure 2: The SDAIN pin of LTC4300-1 is connected to the backplane SDA bus
Once the bus is not connected to the card and the backplane has a stop bit or the bus is idle, LTC4300-1 stops the precharge circuit, activates the input to the output connection circuit, and connects the backplane SDA and SCL buses to the circuit on the card.
Capacity buffer and rise time accelerator characteristics
The key feature of the input-to-output connection circuit is to provide two-way buffering. Figure 3 is an application that takes advantage of this feature. If the 1/O card is directly connected to the backplane, all the capacitors on the backplane and the card will be added directly, making it difficult to meet the rise and fall time requirements. Place the LTC4300-1 on the edge of each card, but isolate the card capacitance from the backplane. For a given 1/0 card, the LTC4300-1 drives the capacitance on the card, and the backplane must only drive the low capacitance of the LTC4300-1. LTC4300-1 further meets the system’s rise time requirements by providing rise time accelerator circuits located on all four SDA and SCL pins. Figure 4 shows the improved rise time provided by the accelerator for the equivalent bus capacitance of 10pF and 100pF.
Figure 3: Multiple I/O cards inserted into a backplane
Figure 4: Rise time accelerator for pull-up capacitors at 10pF and 100pF
The LTC4300-1 allows users to insert the I/O card into a live backplane without destroying the SDA and SCL signals on the backplane of a dual-bus system. In addition, the connection circuit provides two-way buffering to isolate the backplane and the card capacitor rise time accelerator circuit to help to meet the rise time requirements.
(Source: Analog Devices)