“The trend in switching power supply design is miniaturization. In the miniaturization design of switching power supply, increasing the switching frequency can effectively improve the power density of the power supply. But as switching frequencies increase, circuit electromagnetic interference (EMI) issues make power engineers even more challenging. This article takes the flyback switching topology as an example to discuss how to reduce circuit EMI from a design perspective.

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Abstract: The development trend of switching power supply design is miniaturization. In the miniaturization design of switching power supply, increasing the switching frequency can effectively improve the power density of the power supply. But as switching frequencies increase, circuit electromagnetic interference (EMI) issues make power engineers even more challenging. This article takes the flyback switching topology as an example to discuss how to reduce circuit EMI from a design perspective.

In order to improve the power density of the switching power supply, the first solution that power supply engineers think of is to choose a MOSFET with a higher switching frequency. By increasing the switching speed, the volume of the output filter can be significantly reduced, so that a higher power level can be achieved per unit volume.However, as the switching frequency increases, the EMI characteristics will deteriorate, and effective measures must be taken to improve the EMI characteristics of the circuit.

The power MOSFET of the switching power supply is installed on the printed circuit board. Due to the stray capacitance and parasitic inductance of the MOSFET traces and loops on the printed circuit board, the higher the switching frequency, the more stray capacitance and parasitic inductance can not be ignored. Since the voltage and current on the MOSFET change rapidly when switching, the rapidly changing voltage and current interact with these stray capacitances and parasitic inductances, resulting in voltage and current spikes that significantly increase output noise and affect system EMI characteristics.

From equations 1-1 and 1-2, it can be known that the parasitic inductance and di/dt form a voltage spike, and the parasitic capacitance and dv/dt form a current spike. These rapidly changing currents and associated harmonics generate coupled noise voltages elsewhere, thus affecting the switching power supply EMI characteristics. Taking the flyback switching topology as an example, the measures to reduce the dv/dt and di/dt of the MOSFET are introduced below.

Figure 1 MOSFET noise source

**1. Reduce dv/dt of MOSFET**

Figure 2 MOSFET equivalent circuit

We are concerned with MOSFET characteristics and the parasitics that affect these characteristics:

In 1-3, the larger the Rg and Cgd, the lower the dv/dt. In 1-4, the lower the Coss, the higher the dv/dt. In MOSFET selection, the parameters of Coss, Ciss, and Crss of MOSFET affect the switching peak size.

It can be seen from the above analysis that we can reduce dv/dt by increasing the MOSFET parasitic capacitances Cgd, Cgs, Cds and increasing the drive resistance value Rg.

Figure 3 Measures to reduce dv/dt of MOSFET

The following effective measures can be taken:

l Higher Cds can reduce dv/dt and reduce Vds overshoot; but higher Cds will affect the efficiency of the converter. MOSFETs with lower breakdown voltage and lower on-resistance can be used (the Cds of such MOSFETs are also lower). But if noise radiation is considered, a larger resonant capacitor (Cds) is required. Therefore, improving Cds requires weighing the relationship between EMI and efficiency;

l Higher Cgd substantially increases the duration of the MOSFET in the Miller plateau, which can reduce dv/dt. But this leads to increased switching losses, which reduces MOSFET efficiency and increases its temperature rise. When Cgd is increased, the required driving current will also increase significantly, and the driver may be burned due to excessive instantaneous current; it is recommended not to add Cgd easily;

l Add an external Cgs capacitor at the gate, but this method is rarely used because it is relatively simple to increase the gate resistance Rg. The effect is the same.

Summarize:

Figure 3 summarizes the dv/dt reduction measures for MOSFETs. When the internal parasitics (Cgd and Cds) of the MOSFET are low, it may be necessary to use external Cgd and Cds to reduce dv/dt. External capacitances range from a few pF to 100pF, which provides designers with fixed values of these parasitic capacitances for reference designs.

**2. Reduce the di/dt in the circuit**

Figure 4 Measures to reduce di/dt of MOSFET

Figure 4 The various di/dt sections present in the MOSFET drive stage have two effects:

l Noise voltage caused by stray inductance at G pole, D pole and S pole

l Noise voltage of primary large loop

l Improvements can be made through the following measures:

l Increase the high frequency capacitor to reduce the loop area

l We can take measures to reduce the PCB loop area of the high frequency potential trip point. Increasing the high-frequency high-voltage DC capacitor C_IP is an effective measure to reduce the PCB loop area and separate the high-frequency and low-frequency loops.

l Reasonable increase of magnetic beads to suppress high frequency current

l In order to additionally reduce the di/dt, a known inductance can be added to the circuit to suppress current spikes and oscillations in the high frequency band. The known inductance is in series with the stray inductance, so the total inductance value is within the designer’s known inductance range. Ferrite beads are good high frequency current suppressors that become resistive over the expected frequency range and dissipate noise energy as heat.

**3. Recommended test plan**

Correct use and selection of measuring instruments and measurement methods can help quickly locate the source of problems. When debugging, the PWR2000W variable frequency power supply is used to provide the input voltage, which can protect the circuit in time when the circuit under test is abnormal. Ordinary test probes are prone to introduce additional parasitic inductance, causing noise to be reflected in ordinary probes, causing oscillation and introducing uncertainty to the measurement. Using the ZP1500D high-voltage differential probe introduced by our company, its input impedance is as high as 10MΩ, and the CMRR can reach more than 80dB, which is suitable for direct measurement of MOSFET. ZDS4000 series oscilloscopes are data mining oscilloscopes with 500M analog bandwidth and 512M storage depth, which fully meet the needs of depth noise measurement. Figure 5 is a block diagram of the recommended reference test scheme.

Figure 5 MOSFET noise test scheme

l MOSFET current test waveform

As shown in Figure 5, ferrite beads are added to the G-pole, S-pole and RCD circuits for optimization. Measurements were performed using current probes ZCP0030 and ZDL6000 oscilloscope recorders.in input[email protected]