# How to Achieve Higher Resolution, Fewer Bit Ternary DACs

I was delighted when reader and DI contributor Jim Brannan suggested writing his base-3 DAC design. Like Charlieplexing, his idea is to use tri-state outputs to screw more information out of the pins than just “0” and “1”! For example, a four-bit DAC could theoretically produce 34 (81) levels instead of the usual 16. Five bits will actually match the regular eight-bit performance (243 levels), although the exact implementation may be more. Difficulty than a regular binary DAC, especially as the resolution increases.

I was delighted when reader and DI contributor Jim Brannan suggested writing his base-3 DAC design. Like Charlieplexing, his idea is to use tri-state outputs to screw more information out of the pins than just “0” and “1”! For example, a four-bit DAC could theoretically produce 34 (81) levels instead of the usual 16. Five bits will actually match the regular eight-bit performance (243 levels), although the exact implementation may be more. Difficulty than a regular binary DAC, especially as the resolution increases.

As usual, I googled around for prior art and, yes, found two pages describing a similar beast. Jim took a look and decided he had nothing to add, so… no “design philosophy”. But I think the concept is worth promoting. Jim also has his own unique approach.

Before continuing, maybe take a moment to imagine how a ternary DAC might be implemented. Maybe you’ll come up with a new variant and then figure out the idea below.

Ok, here is my own implementation idea:

Figure 1 A summing amplifier with a mid-supply reference implements a radix-3 DAC.

Actually, my initial thought was to put the (+) input of the amplifier at -VDD, but then I realized that a floating output would be pulled to that negative supply, probably clamped at -0.7V, and would normally not work. The VDD/2 reference means the 0,1,2 state corresponds to the 0,Z,1 output (“Z” means high impedance and/or input mode).

Another hardware issue is that some microcontrollers can draw too much supply current when the input is on mid rail, so make sure this isn’t an issue, disable digital input mode, or use a pin that can be set as an analog input.

Driving a ternary DAC would require a lookup table or binary to ternary conversion routine. In most cases, unless the pin mode and value can be set within one write cycle, the DAC output will glitch after changing its settings.

Jim’s discontinued “Design Idea” uses a passive “R-2R” type DAC, and he wrote software to search for many combinations of resistors. There is no way to create a perfectly linear DAC, his solution is to use a lookup table and the performance is somewhat uneven.

Josh Bowman describes his thoughts on 3-ary DACs on his blog. The structure is R-2R-ish, where smaller value resistors split the power supply to generate a mid-scale “Z” value.

Figure 2 Josh Bowman’s passive ternary DAC

As shown below, there are redundant values ​​in the design that can be calibrated.

Figure 3 Raw and calibrated INL performance

There are also some base-3 based DAC designs discussed on this Arduino forum which are variations on the above designs.

If trying a ternary DAC implementation, please restate your experience below. We wish to know this. Remember, as with all these simple DAC designs, power supply noise is passed to the output.