The 138 decoder is an important practical application device, and there are many models for the 138 decoder. The explanation of 138 decoder in this paper is mainly based on 71hc138 decoder. The main content is: 71hc138 decoder introduction + function introduction + principle analysis + application.
1. Introduction to 74hc138
The 74HC138 is a high-speed CMOS device, and the 74HC138 is pin-compatible with the low-power Schottky TTL (LSTTL) family. The 74HC138 decoder accepts 3-bit binary weighted address inputs (A0, A1 and A2) and, when enabled, provides 8 mutually exclusive active-low outputs (Y0 to Y7).
The 74HC138 features three enable inputs: two active lows (E1 and E2) and one active high (E3). The 74HC138 will keep all outputs high unless E1 and E2 are set low and E3 is set high.
The 74HC138 is a high-speed silicon-gate CMOS decoder suitable for memory address decoding or data routing applications. 74HC138 works in high-performance storage decoding or data transmission systems requiring short transmission delay time. In high-performance storage systems, this decoder can improve the efficiency of the decoding system. When fast enable circuits are used for high-speed memory, the delay time of the decoder and the enable time of the memory are usually less than the typical access time of the memory, which means that the system decoding by Schottky-clamped. The effective system delay caused by the encoder is negligible. HC138 decodes a low-level output from 8 output terminals according to the three-bit binary input code and enabling input conditions. Two active low-level enabling inputs and one active-high enabling input reduce the need for external gates or inverters for expansion, and expansion into a 24-line decoder does not require an external gate; expansion into 32 Line decoder, only need to connect an external inverter. In demodulator applications, the enable input can be used as a data input.
2. Function of 74hc138
The 74HC138 decoder accepts 3-bit binary weighted address inputs (A0, A1 and A2) and, when enabled, provides 8 mutually exclusive active-low outputs (Y0 to Y7). The 74HC138 features three enable inputs: two active lows (E1 and E2) and one active high (E3). The 74HC138 will keep all outputs high unless E1 and E2 are set low and E3 is set high. Using this composite enable feature, only 4 74HC138 chips and 1 inverter can be easily extended in parallel and combined into a 1-32 (5-line to 32-line) decoder. Choose one active-low enable input as data input, and use the rest of the enable inputs as strobes, the 74HC138 can also act as an 8-output demultiplexer, and the unused enable inputs must be kept bound in their respective appropriate active high or active low states.
The above is the schematic diagram of the 138 decoder. Among them, at the 4th and 5th pins of the chip, there is a horizontal bar above the identifiers G2A and G2B, which means that the output of this port is active low (it can be seen that the 4th and 5th pins are connected to GND), and the 6th pin is connected to GND. pin is connected to VCC.
The 74HC138 decoder accepts 3-bit binary weighted address inputs (A, B, and C) and, when enabled, provides 8 mutually exclusive low-active outputs (Y0~Y7). The 74HC138 features three enable inputs: two active lows (G2A, G2B) and one active high (G1). The 74HC138 will keep all outputs high unless G2A and G2B are deasserted and G1 is deasserted.
Its truth table is as follows (can be consulted through the chip manual):
As shown in the notes below the chart: H—high level, L—low level, X—arbitrary level, G2(—) represents the sum of G1A and G2B (in fact, you can see from the schematic diagram that G2A and G2B are together controlling).
Through the truth table, we know that the correct control method is, G1 gives high level, G2 gives low level. Then, by controlling the input values (binary) of the three ABC, the output values (binary) of Y0-Y7 are controlled.
For example, ABC = 000, Y0-Y7 = 0111 1111; ABC = 101, Y0~Y7 = 1111 1011.
One thing please note:
As mentioned earlier, the 138 decoder provides 8 mutually exclusive (Y0-Y7, 8 pins do not affect each other) low-level output, but the output is 1 except the one selected by the ABC address. This is because a NAND gate is connected in front of each output port inside the chip, so the level of the output terminal is inverted.
The logic diagram of the 74HC138 decoder is attached below:
In front of each output port, you can see that there is a NAND gate circuit (simple digital knowledge), we can assign values to ABC in the logic diagram, then check the output of Y0~Y7, and then check with the truth table one time.
So far, it may have been seen that one of the functions of the 138 decoder: as shown in the schematic diagram, the three pins of P2.5P2.6P2.7 control 8 outputs! But you will ask , each time the output will be 7 high levels and 1 low level.
3. Application of 74HC138
Generally in the single-chip microcomputer circuit, in order to master more devices, it is necessary to use some core digital chips. This digital chip uses complex output logic to master the input logic, such as the 74HC138 three-eight decoder, the picture shows 74HC138 in our One use on the rationale diagram.
Analyzing from this name, the 38 decoder is to translate 3 output forms into 8 input forms. As can be seen from Figure 3-15, 74HC138 has 1 to 6 output pins in total, but the three pins 4, 5 and 6 are enable pins. The enable pin is the same as the OE pin of the 74HC245 we talked about earlier. If these three pins do not meet the regular output request, Y0 to Y7, no matter what the level state of the 1, 2, and 3 pins you output, Always high. So if we want this 74HC138 to work normally, the ENLED output must output a low level, and the ADDR3 output must output a high level. These two positions are mostly enable control ports. I don’t know if everyone can remember that the program in our second lesson has such two sentences ENLED = 0; ADDR3 = 1; is to master and enable the 74HC138.
Most of these logic chips have enable pins, and if the enable meets the requirements, then the control logic will be discussed next. Regarding the pins of digital devices, if one pin outputs the time division, there are two forms of 0 and 1; for the time division of two pins output, there will be four forms of 00, 01, 10, and 11, then about When there are 3 outputs, there will be 8 forms. Everyone can see the truth table below – Figure 3-16, in which the output is in the order of A2, A1, and A0, and the input is from Y0, Y1. . … .Y7 order.
In any output mode of 74HC138, as long as one input pin is low, the other pins are mostly high. In the following circuit, we have seen that the master terminal of the base of the main switch transistor Q16 of the 8 small LED lights is LEDS6, that is, when Y6 inputs a low level, you can keep the transistor Q16 and input it from the wish on the right. As a consequence, we can deduce that the output form of our A2, A1, and A0 should be 110, as shown in the following figure:
Then we will go through the whole process of lighting up the LED light. First, look at the 74HC138. We need to make the LEDS6 low to turn on the transistor Q16, so ENLED = 0; ADDR3 = 1; to ensure that the 74HC138 is enabled. Then ADDR2 = 1; ADDR1 = 1; ADDR0 = 0; This ensures that the switch of transistor Q16 is conservative, and the 5V power supply is applied to the LED.
The left side of the 74HC245 is controlled by the P0 port. We make the P0.0 pin equal to 0, that is, DB_0 is equal to 0, and the right side of DB0 is equal to DB_0, which is also 0, so there are 8 small LED lights in this row. , as long as there is a voltage difference between the small light on the far right and 5V, if there is a voltage difference, the current will flow, and if the current flows through our LED2, it will light up.
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