Empirical multi-channel phase noise model validated in a 16-channel demonstrator

[Introduction]This paper details a systematic approach to predicting phase noise in large multi-channel systems and compares the predicted values ​​with those measured on a 16-channel S-band demonstrator. This analysis method is based on a small set of measurements and can be used to estimate correlated and uncorrelated noise contributions. With just a few measurements, phase noise can be predicted over a wide range of conditions. The point is that any specific design requires its own system noise analysis, and the 16-channel demonstrator provides a specific design example as a basis. This article discusses assumptions and associated limitations based on the 16-channel demonstrator, including when this assumption applies and when additional noise terms need to be added due to increased system complexity. This article mainly describes how to implement phase noise optimization in RF systems.1–6 Where appropriate, references are provided describing the rationale used in this analysis.

Introduction

Phase noise is an important performance metric for all RF system designs. In large multi-channel RF systems such as phased arrays, where the channels are correlated with each other, one of the goals is to improve dynamic range from the array level using a correlated combination of distributed receivers and transmitters. Achieving this goal presents a systems engineering challenge: factoring out the correlated and uncorrelated noise terms in the system. This article presents a systematic method for estimating the phase noise of a 16-channel RF demonstrator to help system engineers develop an analytical method for evaluating the noise performance of large systems.

Signals in a phased array contain both channel-uncorrelated noise terms and channel-correlated noise terms. The additional noise of distributed components is irrelevant. However, signals shared by distributed components generate correlated noise components. The challenge is: how to quickly identify correlated noise terms in the architecture. Common or shared content can cause correlated noise in the channel. Examples include shared LOs, clocks, or power supplies. Addressing these noise terms becomes difficult as system complexity increases. Therefore, it would be of great benefit to system designers building next-generation systems to be able to redraw the architecture from a noise perspective using an intuitive approach and to quickly identify relevant noise contribution terms.

In this article, we demonstrate the method using a 16-channel S-band system, demonstrating that phase noise can be predicted fairly accurately for many other channel combinations using only a few empirical measurements. The key point for this empirical model is that some actual measurements are required. It is not easy to go directly into large multi-channel phase noise estimates (with decent accuracy) from component simulation. However, using only a few measurements, both correlated and uncorrelated noise terms can be extracted, making multi-channel estimates more accurate. Our measurements matched estimates (within 1 dB) to measurements from a 16-channel S-band demonstrator.

Empirical multi-channel phase noise model validated in a 16-channel demonstrator

Figure 1. 16-channel demonstrator: The platform contains four AD9081 chips. Each AD9081 chip contains 4 RF DACs and 4 RF ADCs, providing a total of 16 transmit and 16 receive channels.

Background on the Summation of Correlated and Uncorrelated Noise

In free space or RF signal processing combined signals, the noise added to each signal is

Empirical multi-channel phase noise model validated in a 16-channel demonstrator

where c represents the correlation coefficient, ranging from –1 to +1. If c = –1, the noise is eliminated; if c = 0, the noise is uncorrelated; if c = 1, the noise is completely correlated.

Assuming that calibration is used to consistently merge the main signal, the main signal will increase at a level of 20logN, where N is the number of channels.

• If the noise term is uncorrelated (c = 0), the noise increases by 10logN. As the signal level increases at a rate of 20logN (10logN greater than the noise rate), the SNR improves by 10logN.

• If the noise term is correlated (c = 1), the noise, like the signal, increases at a rate of 20logN, so the SNR will not improve. This is not an ideal result for a distributed system.

● In the noise cancellation circuit, a negative correlation coefficient will be generated. This case is written down to supplement Equation 1, but will not go into detail.

In fact, large distributed systems contain partially correlated noise components in the channel. Therefore, a method for developing a practical and intuitive system-level noise model is needed.

16 channel demonstrator

To evaluate the latest high-speed data converters in a multi-channel environment, a 16-channel direct S-band RF sampling platform was developed. The platform contains four AD9081 MxFE® (mixed-signal front-end) chips. Each AD9081 chip contains 4 RF DACs and 4 RF ADCs, providing a total of 16 transmit and 16 receive channels.

The 16-channel evaluation platform is named Quad-MxFE because it has 4 MxFE chips. The overall block diagram and board pictures are shown in Figure 1 and Figure 2, respectively.

Empirical multi-channel phase noise model validated in a 16-channel demonstrator

Figure 2. The Quad-MxFE is a 16-channel demonstrator.

Multichannel Phase Noise Model

The block diagram of the 16-channel development platform shown in Figure 1 shows its functional scope. As you can see from the figure, it is not clear at first how to look at the part of the noise caused by correlated and uncorrelated noise components. There is a need to provide a way to consider the system architecture from a noise perspective. A sketch can be used to indicate noise terms that are present on all channels, noise terms that are related to certain groups of channels, and noise terms that are completely independent of the channel. Figure 3 is an illustration of a 16-channel development platform, dividing noise terms into three categories.

Empirical multi-channel phase noise model validated in a 16-channel demonstrator

Figure 3. Figure 1 redrawn from a clock phase noise perspective.

● Clock Noise: Quad-MxFE provides options for multiple clock configurations. The specific configuration used needs to be explained in the phase noise model. Our tests used 1 common low phase noise clock across all channels, or 4 independent distributed ADF4371 phase-locked loop (PLL) frequency synthesizers as clock inputs to each of the 4 MxFEs. For a single common clock, this noise is related to all 16 combined channels. For the case of using 4 ADF4371 PLLs (1 MxFE 1), the PLL noise is related to each MxFE but not across the MxFEs, while the reference noise is related across all channels.

○ Peter Delos’ article titled “System-Level LO Phase Noise Modeling for Phased Arrays with Distributed Phase-Locked Loops” summarizes analytical methods for dealing with distributed phase-locked loops. The analysis method used in this reference describes the reference frequency, the noise components of the distributed system, and the PLL circuit, as well as the effect of the PLL loop bandwidth.

● Correlated noise due to each MxFE: This is the noise from the MxFE, associated with each channel in the MxFE. In this analysis, the noise associated with each MxFE includes additive noise commonly found in each chip, as well as power-supply effects commonly found in individual channels inside the chip.

● Uncorrelated noise per channel: This is the difference in noise from different channels. Includes the DAC core and all amplifier additive phase noise. In Equation 2, this term is labeled TXNoise.

From the stated phase noise contributing components, the phase noise summation can be calculated as follows.

Empirical multi-channel phase noise model validated in a 16-channel demonstrator

Next, some additional details are provided on how to simplify this model for this testbench.

● Power supply effects: In low phase noise designs, power supply phase noise is an important factor to consider. See the articles “Supply Modulation Ratio Demystified: What’s the Difference Between PSMR and PSRR” and “Improved DAC Phase Noise Measurement Enables Ultra-Low Phase Noise DDS Applications.” In this article’s analysis, the power supply Effects are treated as sub-terms of the noise term captured in Equation 2. If power supply noise is the dominant source of phase noise in an IC and is spread across all channels, then this effect needs to be accounted for as a correlation term like the correlated noise due to each MxFE used earlier in this article.

• Reference oscillator noise: In large systems, the reference oscillator noise contribution needs to be distributed as described in the article “System-Level LO Phase Noise Modeling for Phased Arrays with Distributed Phase Locked Loops”. This test bench uses a very low phase noise voltage reference, which produces a noise component that is much lower than the other components, so it is not specified in the noise sum formula.

Validate the model with measurements

After the combined phase noise model was introduced in Equation 2, the next question was “How do I get the value of the noise contribution component used in the equation?” When using the Quad-MxFE test bench, the measured values ​​can be used to extract the required information:

● Absolute phase noise of the clock source

● Additional phase noise for channels of different MxFEs

● Additional phase noise for channels of the same MxFE

The test setup and measurements are shown in Figure 4. Figures 4(b) and 4(c) provide additional noise measurements with the common clock source removed. When measuring the additive phase noise in a single MxFE, the correlated noise across channels in the MxFE is also removed. However, when measuring additional phase noise across the MxFE, the associated noise in the MxFE is included in the measurement.

Empirical multi-channel phase noise model validated in a 16-channel demonstrator

Figure 4. Three measurements were used to validate the phase noise model.

The final step is to change the measurement data to the three terms used in Equation 2 as follows:

1. Clock Noise = Clock Phase Noise Measurement (Figure 4(a)) + 20log (FOUT/FCLOCK)

2. Correlated noise due to each MxFE = additional phase noise across MxFEs (Fig. 4(b)) – additional phase noise for generic MxFEs (Fig. 4(c)). Note that for this calculation, it needs to be converted to linear power, then subtracted, and then converted back to dB, giving 10log(10^(Additional Phase Noise Across MxFE/10) – 10^(Additional Phase Noise of Universal MxFE /10))

3. TxNoise = additional phase noise of the generic MxFE (Figure 4(c)).

Additional note on additional phase noise measurements: We found that the noise terms for terms 2 and 3 above also scale with frequency when using this hardware. When converting to other frequencies, an additional 20log(FOUT/FMEAS) is required. This is not the case with all hardware, and each design needs to be evaluated individually.

Measurement Case 1: General Purpose Low Phase Noise Clock

A low noise 12 GHz clock was used throughout the 16-channel demonstrator when performing this measurement. The clock source is SMA100B, which is injected into the external clock injection node as shown in Figure 1. Conditions shown are for 3.2 GHz transmit output frequency.

As can be seen from Figure 5(b), the correlated noise across the MxFE is the most dominant contributing component. This noise contribution component increases when MxFE is added to the system and is then limited by the common clock source. Depending on the shape of the curve for each contributing component, adding just a few points to the curve is not enough to make an accurate prediction, so we found it best to use the data in Figure 5(b) directly in Equation 2. Then, a series of calculations are performed to validate the model. As can be seen from Figures 6 to 8, the predictions provided by this model are very accurate.

Empirical multi-channel phase noise model validated in a 16-channel demonstrator

Figure 5. a) Measurements used to validate the phase noise model, b) Calculated phase noise contribution components used in the model. This is for the case where one clock is shared by all MxFEs.

Empirical multi-channel phase noise model validated in a 16-channel demonstrator

Figure 6. Measured and model predicted values ​​for 16 channels at 3.2 GHz.

Empirical multi-channel phase noise model validated in a 16-channel demonstrator

Figure 7. Measured and model predicted values ​​for 8 channels at 3.2 GHz. The difference between the two figures is how the MxFE shares the transmit channel.

Empirical multi-channel phase noise model validated in a 16-channel demonstrator

Figure 8. Measured and model predicted values ​​for 4 channels at 3.2 GHz. The difference between the two figures is how the MxFE shares the transmit channel.

A few observations about the measured and predicted values ​​are worth noting. In many cases, the predicted value is almost identical to the measured value. In some cases, the measured value was slightly lower than the predicted value. We acknowledge this, but cannot give an accurate description. The plot on the left of Figure 8 provides a potential indicator. When zooming in on the plots, we see that the predicted values ​​match the two measured examples, but the measured cases have slightly higher values. It may be that in the AD9081 chip, the correlated noise caused by each MxFE is not exactly the same, causing some differences. Some of the simplifying assumptions described in Section 5 may also be responsible for the discrepancy. In these examples, the predictions are fairly accurate, and we think this approach is valid for this design.

Measurement case 2: Distributed PLL per MxFE

In this measurement, a separate ADF4371 was used for each of the 4 MxFEs, as shown in Figure 1. The ADF4371 locks onto a low phase noise 500 MHz reference and is set up to provide a 12 GHz output. Figure 9 shows the measurements and noise contribution components used to validate the model.

Empirical multi-channel phase noise model validated in a 16-channel demonstrator

Figure 9. A) Measurements used to validate the phase noise model when using a separate ADF4371 chip as the clock input source, b) Calculated phase noise contribution components used in the model. This is the case for the distributed PLL for each MxFE.

In this example, the PLL is the dominant noise source, and the noise component contributed by the MxFE is much lower than the clock noise. As shown in Figure 10, the combined noise improves accordingly depending on the number of PLLs used by the distributed system.

Empirical multi-channel phase noise model validated in a 16-channel demonstrator

Figure 10. Measured and model-based predictions at 3.2 GHz after combining multiple phase-aligned transmit channels using the ADF4371 as the clock source for each MxFE.

in conclusion

This paper shows an empirical model capable of predicting phase noise in the combined channel with considerable accuracy. The premise of using this method is to first view the system from the point of view of the noise source and redraw the block diagram to see both correlated and uncorrelated terms.

We also highlight the word “empirical”, which means that the proposed method is validated by observation or experience, not by theory or pure logic. For the phase noise example, the point made is that to evaluate the region and contributing components, some measurements and observations are required. With this knowledge in mind, system noise can be calculated systematically.

The data and formulas used in this article are only applicable to this hardware to a certain extent, based on the observations described earlier. However, this method can be used for any multi-channel system. A more general block diagram is shown in Figure 11. Introducing the system reference oscillator and then plotting the clock and LO distributions against channel-level hardware provides a more intuitive view of the sources of noise contribution in large systems.

Empirical multi-channel phase noise model validated in a 16-channel demonstrator

Figure 11. Schematic diagram of a generic phased array drawn from a phase noise perspective. Each signal contains noise terms, which are combinations of noise components distributed in the array. After redrawing the system diagram from this perspective, it is easier to show traces of correlated and uncorrelated noise at the system level. If the designer first draws the system reference oscillator and then draws the clock and LO distributions against the channel-level hardware, it is more intuitive to visualize the sources of noise contribution in large systems.

Reference circuit

1 Peter Delos. “System-Level LO Phase Noise Modeling for Phased Arrays with Distributed Phase-Locked Loops”. Analog Devices, Inc., November 2018.

2 Peter Delos and Mike Jones. “Digital Arrays Using Commercially Available Transceivers: Noise, Spurious, and Linearity Measurements.” IEEE Phased Array Conference, October 2019.

3 Peter Delos. “Power Modulation Ratio Demystified: How Is PSMR Different From PSRR?” Analog Devices, March 2019.

4 Peter Delos and Jarrett Liner. “Improved DAC Phase Noise Measurement Enables Ultra-Low Phase Noise DDS Applications”. Mock Conversations, Volume 51, Issue 3, August 2017.

5 Peter Delos. “Phase Locked Loop Noise Transfer Function”. High Frequency Electronics, January 2016.

6 Peter Delos. “Transceivers Using External Local Oscillators: Lower Phase Noise for Better RF Performance”. Analog Devices, Inc., October 2019.

Michael Jones, Travis Collins, Charles Frick. “Integrated Enhanced DSP on DAC/ADC IC Improves Wideband Multichannel Systems”. Analog Devices, Inc., May 2021.

“2-Port Residual Noise Measurement”. Rohde & Schwarz Application Note.

Source: ADI

By Peter Delos and Michael Jones

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