Design of Universal Multi-DSP Target System Based on Fixed-point DSP Series ADSP2181 Chip

With the development of large-scale integrated circuits, real-time digital signal processing technology based on Digital Signal Process (DSP) is developing rapidly, and has been widely used in image processing technology, voice processing, intelligent instrumentation , biomedicine and engineering, communication, automatic control and other fields. ADSP produced by Analog Device Company is a kind of DSP which is widely used, and its typical products are fixed-point ADSP2181 and floating-point ADSP21060.

1 Overview

With the development of large-scale integrated circuits, real-time digital signal processing technology based on Digital Signal Process (DSP) is developing rapidly, and has been widely used in image processing technology, voice processing, intelligent instrumentation , biomedicine and engineering, communication, automatic control and other fields. ADSP produced by Analog Device Company is a kind of DSP which is widely used, and its typical products are fixed-point ADSP2181 and floating-point ADSP21060.

In many practical systems, multi-chip DSPs need to be cascaded for processing. Therefore, ADSP2181 is often cascaded and used in actual systems. We designed a general-purpose multi-DSP target system based on ISA bus. This system can be used for early research and development and hardware platforms for various algorithms. It shortens the development cycle of actual systems. , project pre-research, etc. are of great significance and application value.

2. The composition of general multi-DSP target system

The general multi-DSP target system is composed of 6 slices of ADSP2181, 2 slices of A/D converters and FPGA that realizes the logic function. Its principle block diagram is shown in Figure 1.

 Design of Universal Multi-DSP Target System Based on Fixed-point DSP Series ADSP2181 Chip

(1) Processing system

The whole processing system consists of 6 DSPs, which completes the acquisition and data processing of the 2-channel analog signals. This system adopts the more typical fixed-point DSP series ADSP2181 from Analog Device Company. The transmission and reception of serial port data and the transmission and reception of frame synchronization signal between two adjacent DSPs are connected respectively, and the data transmission adopts automatic buffering. .

(2) System input

The analog signal input by the system is completed by 2 serial A/D converters with a precision of 12b, the sampling rate is up to 400kS/s, and the input analog quantity is a unipolar (0-2.5V) signal. The analog signal is sent to the first DSP in serial mode after A/D converter.

(3) Timing control

The system timing control is realized by FPGA (Field Programmable Gate Array, Field Programmable Gate Array). The system adopts Altera’s FPGA chip EPFl0K10.

① Generate ISA bus address decoding and control for each DSP access;

② Generate the control signals IAL, IWR, IRD and IS required to access the DSP through the IDMA port;

③ Generate the reset signal of each DSP;

④ Generate control signals CLK (serial port clock) and CONV (conversion control) that meet the timing requirements of the A/D converter.

In addition, FPGA also completes the control sequence required for data transmission between DSP and ISA bus, effectively ensuring the reliability of data transmission.

3. Hardware design of general multi-DSP target system

(1) Address allocation and implementation of the target system

Each DSP target board only occupies one group of port addresses, and each group has four addresses: data port, address port, reset port and control port. The starting address of the group is selected by the 4b jumper switch. If the switch value is set to n, the starting address of the board is 360-4×n (referred to as port), and the other three port addresses are port+2 and port+4 respectively. , port+6. The logic shown in Figure 2 is used in the FPGA to realize the dynamic allocation of the port address of the target system board.

The data port port is used to realize the read and write operations to the internal memory of the DSP, and complete the data transmission between the DSP and the host computer.

The address port port+2 is used to provide the starting address of the internal program memory area (PM) or data memory area (DM) of the DSP when reading and writing to the DSP.

The reset port port+4 is used to reset the DSP to realize the soft reset of the DSP.

The control port port+6 is used to select the DSP to be operated.

(2) Formation of control signals

Six DSPs on the target board occupy the same port address. When the system is working, any data area of ​​any DSP can be read and written. The chip select signal to the DSP is realized through the operation of the control port. When A2A1=11, it corresponds to the control port of the DSP, and the lower 3 bits of the data line (DATA[2..0]) are used to designate one of the six DSPs.

4. Download software design

ADSP2181 integrates a 16-bit IDMA port that can access its internal memory. The host can access any unit of program memory and data memory in ADSP2181 through this port, and realize operations such as downloading files and transferring data to DSP. The process is completed by the operation of the host computer to the IDMA port of the DSP. In this paper, the download software of the general multi-DSP target system based on VB is designed, and various operations are performed on the target system through the host computer.

(1) Port selection Select a group of port addresses, which should be consistent with the port address of the target board;

(2) Processor selection Select the processor number (1# ~ 6#) to be read, written and downloaded;

(3) Download file selection Select the program to be loaded into the specified DSP;

(4) Download and execute the download operation, and automatically check whether the loading is successful, if not, reload;

(5) The read processor selects to call the read processor module to read the contents of the designated unit of the selected processor;

(6) The write processor selects to call the write processor module to write data in the designated unit of the selected processor.

5 Conclusion

The general multi-DSP target system fully takes into account the characteristics of ISA bus and fixed-point ADSP2181 in address allocation, and adopts dynamic address allocation technology, which effectively saves system resources. The download software can perform file download, read, and write operations on one or more DSPs, which greatly enhances the versatility and flexibility of the system. The system can be used for hardware platforms and early research and development of various algorithms, and has high application value.

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