Design of data acquisition system based on dual-channel high-speed and high-precision A/D converter and PCIe bus

This paper introduces the design technology of ultra-high-speed signal acquisition card based on PCIe high-speed serial bus and FPGA controller, and realizes key technologies such as uninterrupted sampling and continuous transmission. The collected signal spectrum is shown in Figure 6. The acquisition card has been applied to a radar reconnaissance and jamming system, and has achieved good results and has important practical value.

Authors: Wang Wei, Fu Qixiang

In the radar countermeasure system, it is necessary to conduct real-time frequency measurement of the radar signal, and can store the frequency of the signal of interest, so as to provide the frequency measurement result and the frequency storage data for the false target deception jamming or suppressing the jamming. Digital frequency measurement is one of the fastest-growing frequency measurement technologies today. One of the key technologies for digital frequency measurement and frequency storage is ultra-high-speed, high-precision, and uninterrupted signal acquisition technology. The continuous improvement of sampling rate and precision makes data transmission and storage increasingly become the technical bottleneck of data acquisition system. At present, most high-performance data acquisition cards are based on PCI, CPCI, VME and other buses, and the maximum continuous transmission rate is difficult to exceed 400 MB/s. There is a memory with a certain capacity. When the memory stores a certain amount of data, it stops collecting and starts uploading data. After uploading, it restarts the collection, and the cycle continues. The literature also proposes a pipeline mode of collection and transmission to improve the efficiency of collection. Although these working modes can also meet the requirements of most data collection, in a very dense signal environment, the alternate working mode will reduce the probability of reconnaissance and interception and reduce the efficiency of interference. Based on the above reasons, this paper discusses a data acquisition card based on PCIe bus, which can not only achieve 800 MHz/s sampling rate and 14 bit sampling accuracy, but also has the ability of uninterrupted acquisition and real-time uploading (in frequency measurement only Take the resolution of 8 bits, and take the resolution of 14 bits when storing the frequency, which is programmable according to the total data volume of the system). The acquisition card can be used in conjunction with a high-speed signal processor to form a channelized digital frequency measurement and frequency storage system. The schematic diagram of the dual-channel system is shown in Figure 1.

Design of data acquisition system based on dual-channel high-speed and high-precision A/D converter and PCIe bus

1 Overall system design

The design of this acquisition card mainly includes ultra-high-speed A/D converter module, clock generation module, large-capacity memory module and FPGA-based control module. As shown in Figure 2, the analog signal to be collected is amplified to an appropriate level range after signal conditioning, and sent to two A/D converters working in cross-sampling mode. After conversion, the digital signal is directly sent to the FPGA controller. After the signal level conversion data buffer is implemented in the FPGA, it is first stored in the dynamic memory of channel A. When the memory of channel A is full, the data is immediately transferred to the memory of channel B, and the data upload operation is started at the same time, and the data of the memory of channel A is transferred. It is uploaded to the host for storage or transferred to the signal processing board by DMA; when the B-channel memory is full, the data storage is immediately switched to the A-channel memory, and the upload operation of the B-channel memory is also started, and the cycle is repeated. Since the transmission rate of the PCIe interface is greater than the signal acquisition rate, data loss can be guaranteed.

Design of data acquisition system based on dual-channel high-speed and high-precision A/D converter and PCIe bus

2 Design of dual-channel high-speed and high-precision A/D converter

The high-speed A/D converter module is the front end of the capture card, and its design will determine the performance index of the capture card. The function of the signal conditioning part is to perform low-noise amplification, filtering and other processing on the input signal under the premise of ensuring that the signal to be tested is not distorted. Since the signal to be collected is a high-frequency signal, impedance matching and pre-amplification are required, and a low-distortion active amplifier or a radio frequency transformer can be selected. The advantage of the active amplifier is that the input dynamic range is large, and the gain can be adjusted within a certain bandwidth. The amplitude of the signal is limited and it introduces insertion loss to the system. Considering the requirements of system design indicators, this system selects TI’s THS4509 amplifier as the signal conditioning device. This operational amplifier has very good broadband characteristics. When the gain is set to 10 dB, the -3 dB bandwidth can reach 1900 MH-z. And the adjustable output common-mode voltage makes THS4509 very suitable for high-performance signal acquisition systems; considering that it is difficult to obtain a single-chip A/D converter on the market, it can achieve a sampling rate of 800 MHz/s and a resolution of 14 bits. Therefore, two pieces of ADS5474 are used as the A/D converters of this acquisition card. The maximum sampling rate of the A/D converters is 400MHz/s, the resolution of 14 bits, and the bandwidth of -3 dB reaches 1 400 MHz. The signal output of LVDS level can be directly connected to the FPGA processor, which is convenient for system design.

Design of data acquisition system based on dual-channel high-speed and high-precision A/D converter and PCIe bus

The signal acquisition is continuous, and the data upload is intermittently acquired by the host software through DMA. Therefore, a large-capacity memory needs to be designed to cache the data. At the same time, in order to achieve the purpose of uninterrupted acquisition, two storage areas are designed to use ping-pong cache. In other words, when one storage area is used to cache the high-speed data of the A/D converter, another storage area is used to upload the previously stored data. The large-capacity memory adopts Micron’s memory module MT4HTF3264HY-53E. The memory module has a capacity of 256 MB and a data bus width of 64 bits. It adopts SODIMM package form, and the data access bandwidth can reach up to 4.3 GB/s, which is far beyond the requirements of this system. .

When the acquisition card works at a maximum sampling rate of 800 MHz/s and a resolution of 14 bits, the converted data rate will reach 1.6 GB/s, which brings great pressure to subsequent data transmission. Commonly used buses such as PCI, PXI, etc. can no longer meet such high speed requirements. This system uses 8-channel PCIe bus to achieve high-speed data transmission, each channel runs at a rate of 2.5 Gb/-s, and uses 8b/10b codec In this way, the total data bandwidth of about 2 GB/s can be obtained, which can meet the requirements of real-time data transmission.

Design of data acquisition system based on dual-channel high-speed and high-precision A/D converter and PCIe bus

3 Design of PCIe control interface based on IPCORE

The PCIe interface control circuit is the key module of the acquisition card, and the data interaction between the host and the acquisition card is completed through the PCIe control core. PCIe has a variety of component types, each with complex system-level compromises to meet stringent design goals. In order to speed up product development, this design uses Xilinx’s Logicore IP for PCI Express to design the PCIe high-performance interconnect design interface. This IP core occupies less FPGA resources and consumes less power, including physical layer, data link layer, Transport protocol layer and configuration space. As shown in Figure 3, there is a clear division of labor between layers, which is more abstract than the non-layered protocol description of the PCI bus. The transmission protocol layer and the data link layer are responsible for grouping the collected data in batches. Corresponding checksum frame information is appended when passing between layers. The PCIe standard uses the acknowledgment retransmission mechanism, including corresponding acknowledgment delay and retransmission delay timers at the data link layer. These two timers are greatly affected by the delay between the serial deserialization module and the transmission medium. Transmission delay often causes unnecessary retransmissions, which significantly reduces performance. Therefore, targeted adjustments need to be made in different acquisition environments. The values ​​of the two timers in the design can be configured and modified through the software interface, and the two timers can be dynamically modified by driving the software to achieve the optimization of the acquisition and transmission performance.

4.2 System acquisition timing control

The system control module completes the uploading of the collected data, the issuing and execution of the host command: the system control adopts the control mode of the finite state machine, as shown in Figure 5. When the system is powered on, the controller enters the initialization state by default, and completes the configuration of default parameters, including sampling frequency, sampling depth, trigger mode, clock source selection, analog input range and coupling mode, etc. After the initialization is completed, it enters the idle state. Waiting to receive the host command and execute the operation; after receiving the command to start the acquisition, the controller first connects the data bus input by AD to the data bus of memory A, and starts the DDR2 controller of memory A to perform the write operation; when memory A When it is stored to the depth set by the software or when it is full, switch the AD input data bus to the memory B data bus, start the DDR2 controller of memory B to perform the write operation, and notify the host through DMA interrupt, waiting for the host to upload the memory The data in A; this cycle works repeatedly until it receives the command from the host to stop collecting and then returns to the idle state.

5 Conclusion

This paper introduces the design technology of ultra-high-speed signal acquisition card based on PCIe high-speed serial bus and FPGA controller, and realizes key technologies such as uninterrupted sampling and continuous transmission. The collected signal spectrum is shown in Figure 6. The acquisition card has been applied to a radar reconnaissance and jamming system, and has achieved good results and has important practical value.

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