“In this paper, a multi-channel USB2.0 data acquisition system based on AT91SAMTX is designed, and the AT91SAM7X chip is used as the core to realize the conditioning, conversion, acquisition and transmission of data signals to the upper computer. Because AT91SAM7X has built-in ADC module and USB2.0 device interface, it makes the system design very convenient; at the same time, because there is no need to use a large number of external expansion chips, the hardware cost is greatly reduced, the product volume is smaller, and the stability is also better than that of external expansion chips. There is a substantial improvement.
Author: Wang Pugang, Meng Zhaoli
At present, most of the USB devices used in industry and medical care are connected with a microprocessor using a dedicated USB chip, especially USB data acquisition systems. According to different needs, usually a certain number of A/D converters need to be expanded, and the interface is very complicated. Sometimes it is even necessary to expand the FIFO in order to coordinate different clocks. This design not only greatly increases the cost, but also seriously threatens the stability of the system. This article uses the ARM-based flash microcontroller AT91SAM7X chip developed by Atmel. The chip integrates 8-channel 10-bit ADC and USB2. O device interface, a single chip can complete the design task, avoiding complicated interface circuit design, not only effectively solving the above problems, but also improving the stability of the system to a large extent.
1 Introduction to AT91SAM7X data acquisition main control chip
AT9lSAM7X is a microcontroller based on the 32-bit ARM7TDMI core. AT91SAM7X series microcontrollers have embedded 10/100M Ethernet (Ethernet) MAC, CAN, and full-speed (12 Mbps) USB 2. O. The AT9lSAM7X256, which is designed for a wide range of networked real-time embedded systems, also has a 10-bit analog/digital converter (ADC), 2 serial peripheral interfaces (SPI), synchronous serial interface (SSC), two-wire interface ( TWI), 3 Universal Asynchronous Receiver Transmitter (UART), 1 8-level priority interrupt controller (priority interrupt controller) and numerous supervisory functions. This new 50MIPS MCU has 64 KB of static memory and 256 KB of 25 ns flash memory. This flash memory supports the deterministic processing capabilities required by real-time control systems.
2 Hardware design of data acquisition system
2.1 Hardware design structure diagram of data acquisition system
Multi-channel USB2 based on AT91SAM7X designed in this paper. The O data acquisition system is mainly composed of 6 parts, as shown in Figure 1, which are input signal interface module, multi-channel signal amplification module, signal conditioning module, data acquisition and processing module, USB2. O interface module and host computer module. Among them, the input signal interface module, the multi-channel signal amplification module, and the signal conditioning module mainly complete the isolation and conversion of a 5～+5 V signal of the external standard. Because the ADC of AT91SAM7X allows access to the conversion voltage range of 0 ~ 3 V, so the signal conversion of the above three processes is necessary. The main conversion method used in this system is signal differential amplification, the main part of the data acquisition and processing module and USB2. The O interface module consists of ADC module and USB2 built in AT91SAM7X respectively. O module to complete. Since most of the work is done inside the same chip, the data collection and transmission process can be completed only through simple register settings and data exchange, which optimizes the design of the system to a large extent.
2.2 Introduction of ADC module of AT91SAM7X
The on-chip ADC of AT91SAM7X is based on the continuous register (SAR) model, and 8-channel analog/digital conversion is realized on-chip through an 8-to-1 analog multiplexer. ADC input range is OV～ADVREF. ADC supports two resolutions of 8-bit and 10-bit, and it can be started by software trigger, external ADTRG trigger pin, and internal trigger timer. The accuracy of the ADC can be improved by configuring the ADC clock, start time, and sample and hold time. The ADC is not managed by the power manager and has an interrupt source. If the ADC interrupt signal is used, the interrupt controller (AIC) needs to be configured.
2.3 USB of AT91SAM7X 2. O module introduction
AT91SAM7X has a built-in USB device controller, and the USB device port complies with USB2. O Full-speed device specification, with a communication rate of 12 Mbps. Each endpoint can be configured as one of several USB transmission types. The USB device automatically detects suspend and resume, and stops the processor through interrupts. At the same time, in order to cooperate with the use of USB devices and give full play to its maximum performance, 328 bytes of dual-port RAM is integrated on the chip. One DPR segment of this dual-port RAM is read/written by the processor, and the other DPR segment is USB2. O peripheral read/write, thus effectively guaranteeing the maximum bandwidth of data transmission.
3 Configuration and module programming of AT91SAM7X
3.1 Configuration and module programming of ADC module
The functional block diagram of ADC module is shown as in Fig. 2. The ADC module is a 10-bit analog/digital converter based on the successive approximation register (SAR), which integrates an 8-to-1 analog multiplexer, which can realize 8-channel analog signal analog/digital conversion. Conversion from OV to ADVREF. At the same time, ADC supports 8-bit or 10-bit resolution mode, and the conversion result enters a general-purpose register (ie, channel-specific register) available for all channels. It can be configured as software trigger, external trigger ADTRG pin rising edge or internal trigger timer counter output. The ADC also integrates a sleep mode and conversion sequence generator, and is connected to the PDC channel. These features can reduce power consumption and reduce processor interference. Finally, the user can configure the ADC time, such as start-up time and sample and hold time.
In the system design, the multi-point method is used for A/D conversion, and ADVREF is connected to 3. The reference voltage of OV. For convenience, a single-point conversion is taken as an example to illustrate the configuration and module programming of the ADC module. Of course, before the A/D conversion, the system clock and the overall configuration are necessary. Only the configuration and module programming related to the ADC module are introduced here. Clear all registers related to analog/digital conversion first to ensure that all registers have certain values. The specific configuration process and IAR program code are as follows:
3.2 USB2.0 module configuration and firmware programming
USB2.0 interface module is shown as in Fig. 3. This module needs 2 clocks, namely USB2. O device port clock and main clock. The module accesses the USB2.0 device port through the APB bus interface. Read/write the 8-bit value of the APB register to read/write the dual-port RAM that stores data. External recovery signal is optional, allowing USB to wake up in system mode2. O device port peripherals, and then the host will notify the device requesting recovery. USB2. When the O interface is enumerated, this feature must be processed by the host. In order to keep checking the I/O line of VBUS, the controller of PIO must be programmed first, and this I/O is configured as input PIO mode. USB2. There is an interrupt line in the O device connected with the advanced interrupt controller AIC, therefore, when processing the USB2.0 device interrupt, the advanced interrupt controller AIC must be programmed before the USB2.0 device port is configured.
The USB2.0 interface is used in this system to communicate with the host computer. For the convenience of explanation, here take the upper computer end to transfer the number of 0-9 through the USB2.0 interface, and loop 10 times as an example to illustrate the configuration of the USB2.0 module and the same programming. After the system is initialized, the firmware program sends the numbers from 0 to 9 through the USB2.0 interface, and it ends after 10 cycles. The specific configuration process and IAR program code are as follows:
Note: During the USB2.0 communication interface 121 debugging process, the USB2.0 firmware program must be downloaded to F1ash of AT91SAM7X. This process can be completed by remapping the address of ARM, and then power on the USB2.0 interface again, because the upper computer detects the device only when the device is inserted, and prompts to add the corresponding driver. If the developer only loads the program into RAM during the debugging process, the data will not be saved due to power failure, and the firmware program will not exist the next time the device is inserted. No matter what kind of driver is added to the upper computer, the upper computer will not Data will be received, which will cause the entire debugging process to fail.
3. 3 USB2.0 Windows application program design
The upper computer part realizes the USB communication with the embedded hardware part through the Visual C++++ 6.0 program. During the test, first download the USB2.0 firmware program to AT91SAM7X, plug in the USB data cable, add the corresponding driver according to the prompts, and run the designed Visual C++ 6.0 program directly. The test result is shown in Figure 4.
During the running of the bit machine program, first check the connection of the device, and start to receive the data sent by the USB 2.0 device after confirming the successful connection. Here are the numbers from 0 to 9 that cycle 10 times. As shown in Figure 4, the data has been successfully transmitted to the host computer.
In this paper, a multi-channel USB2.0 data acquisition system based on AT91SAMTX is designed, and the AT91SAM7X chip is used as the core to realize the conditioning, conversion, acquisition and transmission of data signals to the upper computer. Because AT91SAM7X has built-in ADC module and USB2.0 device interface, it makes the system design very convenient; at the same time, because there is no need to use a large number of external expansion chips, the hardware cost is greatly reduced, the product volume is smaller, and the stability is also better than that of external expansion chips. There is a substantial improvement.