Design and implementation of nuclear physics experiment scaler based on FPGA

This paper introduces the principle and realization method of using the modern EDA method to design a common instrument for nuclear physics experiments – the calibrator. The new scaler uses FPGA technology to integrate a large number of circuits in the system, and combines AT89C51 single-chip microcomputer for control and processing, and adds data storage function and RS232 interface to communicate with PC and process experimental data. This paper gives the detailed design schematic diagram of the new scaler and the specific design scheme of FPGA.

Introduction: This paper introduces the principle and realization method of the calibrator, a common instrument used in the design of nuclear physics experiments using modern EDA methods. The new scaler uses FPGA technology to integrate a large number of circuits in the system, and combines AT89C51 single-chip microcomputer for control and processing, and adds data storage function and RS232 interface to communicate with PC and process experimental data. This paper gives the detailed design schematic diagram of the new scaler and the specific design scheme of FPGA.

The scaler is widely used in university experiments. Among them, there are two experiments in the nuclear physics experiment in the modern physics experiment (GM counter tube and β absorption) that use a high-voltage power supply and a scaler. At present, there are existing The equipment generally uses discrete components, which have been seriously aged, the high voltage is extremely unstable, and the maintenance is also difficult; on the other hand, many commonly used functions are obviously lacking, making it difficult for students to maintain experimental classes. To this end, we propose a new design scheme: using EDA for structural design, giving full play to the integration characteristics of FPGA (Field Programmable Gate Array) technology, abandoning many transistors in the original circuit, and successfully implementing a large number of processing circuits in the system. Simplified and intensive, the reliability and stability of the instrument are improved, and it is beneficial to the testing and maintenance of the circuit. The scaler after the improvement scheme not only improves the original functions, but also adds functions such as data storage and RS232 interface, which can easily communicate with the PC interface for data processing, image Display and printing.

1 GM counter principle

Design and implementation of nuclear physics experiment scaler based on FPGA

GM counter tube is a low-pressure gas discharge tube, its function is to convert incident particles (rays) into voltage pulse output. In atomic core physics experiments, it is often used as a “probe” of a counting device to detect rays and their intensity. There are two types of GM counter tubes: a bell-jar type for detecting beta rays and a long cylindrical type mainly for detecting gamma rays. Among them, the working voltage of the bell type beta counter tube is about one thousand V (volts), and the working voltage of the cylindrical type is close to one thousand V (volts).

The ray particles cause gas “avalanche” discharge in the counter tube, which makes the counter tube turn on; the current passes through the load resistor R to form a negative pulse, this pulse signal passes through the capacitor C, and is sent to the scaler for counting through the preamplifier, as shown in Figure 1 shown. Because the counter tube will form a continuous discharge phenomenon after the discharge is terminated, which is extremely harmful to the counter tube, so when the count suddenly increases, the high voltage should be reduced immediately. The improved scaler will automatically control the high voltage source to reduce its voltage. these improvements. This can avoid the problem of counting tube damage that occurred in previous experiments.

2 Principle and hardware implementation of calibration system

The scaler system consists of three modules: the power supply part, the input circuit part and the pulse count Display part. The principle block diagram is shown in Figure 2.

Design and implementation of nuclear physics experiment scaler based on FPGA

The negative pulse generated by the GM counter tube is input to the shaping circuit, which is shaped and amplified to generate a standard TTL signal, which is then counted by the counting and measuring circuit. The timing pulse width gate control circuit controls the pulse width of the count, divided into 6 grades: ×10-3, ×10-2, ×10-1, ×100, ×101, ×102. There are 4 options for time multiplication: ×1, ×2, ×4, ×8. A set of measurement data obtained in this way can be used to describe the law of ray particle generation.

In Figure 2, the display part adopts the method of dynamic display, using the single chip AT89C51 to carry out real-time control and corresponding display data. At the same time, according to the needs, select some measurement data (including the count data and the corresponding high voltage value) and store them in the RAM, and then send the selected data in the RAM to the PC through the RS232 serial port, and process the data through the corresponding processing software. traces, and the corresponding experimental data processing. In order to make the system more integrated, specific time pulse width gating, counting measurement circuit, address decoding and data latching, bus driving and other circuits are integrated into a FLEX10K FPGA. Figure 3 is a detailed circuit block diagram of the system.

Design and implementation of nuclear physics experiment scaler based on FPGA

3 FPGA chip design

3.1 FPGA logic function structure and its overall design

Design and implementation of nuclear physics experiment scaler based on FPGA

In order to simplify the design and realize the integration of a large number of logic circuits in the system, a field programmable gate array device (FPGA) is used in the design. FPGA mainly realizes the following logic functions: timing pulse width gating, counting measurement, address latching, decoding, bus driving and expansion, and digital display control. The top-level structure of its logic function is shown in Figure 4. The FPGA device selects the EPF10K10LC84-4 chip of the FLEX10K10 series of Altera Corporation. The chip integrates 10,000 equivalent logic gates, contains 572 logic cells (LEs), 72 logic array blocks (LABs), 3 embedded array blocks (EABs), and has 720 on-chip registers, which can Realize 6144 bit on-chip memory without occupying internal resources; use high-speed, predictable fast channel connection between internal modules; high-speed, high-fan-out cascade chain and fast carry chain between logic units; chip There are also tri-state networks and 6 global clocks, 4 global clear signals and abundant I/O resources; each I/O pin can be selected as tri-state control or open-collector output, and each I/O pin can be programmed to control each Speed ​​of I/O pins and use of I/O registers.

The development software used by the FPGA is MAX+PLUS II. The software is a super-integrated environment that integrates design input, compilation, simulation and programming; it provides automatic logic synthesis tools, which can synthesize and optimize advanced design descriptions at multiple logic levels, greatly reducing compilation time and speeding up FPGA design and development process. MAX+PLUS II supports various HDL input options, including VHDL, Verilog HDL and ALTERA’s hardware description language AHDL; provides a wealth of library units for designers to call, including all devices of 74 series and a variety of special logic macrocells (macrofunction), and a new type of parameterized giant unit (magafunction).

FPGA design goes through four basic stages: design entry, design compilation, design verification, and device programming. First, the top-level structure diagram is generated according to the logical function of the system, as shown in Figure 4. Then, it is divided into several small modules for next-level design. From this, the logic function is analyzed from top to bottom, the design is compiled from the bottom layer, and waveform verification is performed at each level. When the logic function of the last top-level module meets the system timing requirements in the waveform simulation, device programming can be performed.

Because FLEX10K saves configuration data in SRAM during operation, and SRAM data is easy to lose. The SRAM cell must be loaded with configuration data after the device is powered up, and after configuration is complete, its memory and I/O pins must be initialized. After initialization, the device enters user mode and starts system operation. For FLEX10K series devices, Altera has provided four configuration schemes: EPC1 (or EPC1441) EPPOM configuration method, passive serial method, passive parallel synchronization method, passive parallel asynchronous method. When configuring the device, we first use passive serial. In this way, the device is configured through the download cable, which is suitable for the debugging stage. When the whole system design is completed, the device is configured by EPPOM. The data solidified in the EPROM will configure the FPGA chip when the system is powered on, and the EPROM chip selects EPC1441.

3.2 FPGA unit module design

The FPGA unit is mainly composed of pulse counting module, timing control module, address latch, decoding, bus driver and expansion module. Among them, the pulse counting module and the timing control module are used to measure the counting times of the input pulses; the address latching, decoding, bus driving and expansion modules mainly realize the time-sharing transmission of each data on the bus. The data on the bus includes pulse count data and high-voltage data of the power module, as well as the digital display data from the data bus D0-D7 of the single-chip microcomputer. The address decoding part in this module provides the latch unit chip select signal. Figure 5 shows the top-level circuit diagram of the FPGA.

Design and implementation of nuclear physics experiment scaler based on FPGA

In the specific design, considering that the counting pulse width is 0.1 ~ 100μs, the highest counting rate is 2MHz, that is, the number of counts reaches 7, so the pulse good number module in the design is equivalent to a 7-bit BCD plus counter; and The timing control module is equivalent to a 7-bit BCD down counter. The preset initial value of the down counter is controlled by the timing selection switch, so as to control the time of the number. The CLR signal is a pulse signal generated by the “counting key”, which marks the start of counting, and when the down counter is reduced to 0, the up counter stops counting. This part of the design is completed by calling the library functions provided by MAX+PLUS II with AHDL language combined with graphic input. Address decoding, latching, and bus driver modules are mainly designed by D flip-flops and I/O interfaces. Since the bidirectional input/output port is used in data transmission, the pin port of the Altera chip cannot be used directly, and a tri-state logic gate needs to be added. Therefore, the bus interface part uses these two function prototypes (tri-state door and bidirectional port) for combined design.

3.3 FPGA functional module simulation timing

Design and implementation of nuclear physics experiment scaler based on FPGA

In the whole FPGA design, each unit module is designed only after strict design verification. Here we mainly use the TIMER of MAX PLUS II for waveform simulation to verify the function of each sub-module and determine whether its timing meets the requirements. If the timing is slightly wrong, or even just a small glitch, change the input design immediately. In this way, the design precision is high and the system work is stable. The design can only be completed when each module finally meets the logical functional requirements in time sequence. Figure 6 is the timing simulation waveform diagram of the FPGA after synthesizing the design in the MAX PLUS II environment.

4 MCU software design

The software part is mainly the one-chip computer AT89C51 to control the system and the corresponding data processing. The whole control process is shown in Figure 7.

Design and implementation of nuclear physics experiment scaler based on FPGA

concluding remarks

This paper presents a new design scheme of the GM counting device scaler used in nuclear physics experiments. Under the traditional experimental principle, this scheme has greatly improved the circuit and function of the old instrument. In the design, the EDA design idea is adopted, the AT89C51 single-chip microcomputer is used as the control core of data transmission, and Altera field programmable logic device (FLEX10K series FPGA) is used to integrate the core counting part circuit efficiently and flexibly. The data storage function is added, and the RS232 serial interface for communication with the PC is added, which makes it more intelligent.

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