UCD3138 is the latest generation digital power controller introduced by Texas Instruments, which was officially released in the first quarter of 2012. Compared with the previous generation digital power controller UCD30xx, it has important improvements in many aspects, richer functions and more powerful performance. Based on a switching power supply with hard-switching full-bridge (secondary side adopts full-wave rectification) topology, this paper introduces the hardware design, software configuration and measured data of the cycle by cycle limitation of UCD3138 in detail. While completing the understanding of the above functions, you can also clearly understand the advantages of UCD3138. References are given at the end of this paper.
1Design and implementation of cycle-by-cycle protection function
The cycle-by-cycle protection function is an important improvement of UCD3138 compared to UCD30xx. It aims to realize cycle-by-cycle protection on the primary side, and can achieve fast response and protection in situations such as input voltage surge and output short circuit.
1.1 Cycle-by-cycle functional implementation description
Each DPWM module inside the UCD3138 chip has one and only one cycle by cycle (CBC) hardware module, as shown in Figure 3 below. When the CBC module receives the trigger signal (FAULT), the CBC module will respond immediately to limit the current duty cycle of DPWM A and DPWM B, which realizes the cycle by cycle protection function.
picture1:UCD3138 InternalCBC module
1.2 Hardware Design for Cycle-by-Cycle Functionality
As shown in Figure 2 below, this circuit is a primary current detection circuit. With the help of the current transformer (turn ratio is 100:1), the voltage obtained at the AD04 network reflects the magnitude of the primary current, and the relationship is:. The voltage at this network will be transferred inside the UCD3138 chip through the analog comparator.
picture2: Primary side current detection circuit
1.3 Software Design of Cycle-by-Cycle Protection Function
The software design of the cycle-by-cycle protection function includes several important parts such as the related configuration of the analog comparator AD04, the association between AD04 and DPWM, and the configuration of the cycle by cycle related parameters, which will be explained one by one below.
1) Configuration of analog comparator AD04
The following code completes the setting of the analog comparator threshold, the voltage point that triggers the CBC. The resolution of “ACOMP_D_THRESH” is 19.5mv and the threshold voltage is set to 30 (585mv). After selecting the external resistors (R17, R117), this parameter can be fine-tuned to obtain the appropriate threshold voltage.
FaultMuxRegs.ACOMPCTRL1.bit.ACOMP_D_THRESH = 30;
2) Association between analog comparator AD04 and DPWM
The following code completes the association of AD04 (comparator D in the code) with DPWM0 and DPWM1. That is, when the voltage exceeds the AD04 threshold voltage, the duty cycle of DPWM0 and DPWM1 will be limited.
FaultMuxRegs.DPWM0CLIM.bit.ACOMP_D_EN = 1;
FaultMuxRegs.DPWM1CLIM.bit.ACOMP_D_EN = 1;
3) Blanking time setting
The following code sets the Blanking time. The “BLANK_A_END” bit has a resolution of 4ns, so this code sets the Blanking time to 100ns.
4) The setting of the number of continuous trigger CBCs
The meaning of the following code is that the system will respond after 20 consecutive CBC triggering, which can be shutdown or no action (the specific response mechanism needs to be set in another code).
Dpwm0Regs.DPWMFLTCTRL.bit.CBC_MAX_COUNT = 20;
5) CBC enable
The following code is the key code to enable CBC. When the associated DPWM is configured as Normal Mode, set the following flag to 1 to enable the CBC function.
Dpwm0Regs.DPWMCTRL0.bit.CBC_ADV_CNT_EN = 1;
Dpwm0Regs.DPWMCTRL0.bit.CBC_PWM_AB_EN = 1;
6) Response after continuously triggering CBC
The following code completes the system’s response when CBC is triggered continuously 20 times. When set to 1, the system’s response is to turn off the driver, and the software state machine jumps to Idle mode.
Dpwm0Regs.DPWMFLTCTRL.bit.CBC_FAULT_EN = 1;
1.4 Measured waveform of cycle-by-cycle protection function
When testing the cycle-by-cycle protection function, the secondary overcurrent protection needs to be temporarily shielded. At the same time, in order to fully observe the effect of CBC, set the response action of triggering CBC to not turn off the driver, and the system will run normally. When the system is loaded to 20A and the CBC is triggered, since the system does not turn off the driver, the duty cycle of the primary side of the full bridge will be gradually limited until it becomes the minimum duty cycle.
The measured waveform is shown in Figure 3 below. Since the duty cycle will be limited and reduced without shutting down after CBC is triggered, the output voltage will be gradually pulled down. When the output voltage stabilizes, the duty cycle is limited to a minimum. The width of the minimum duty cycle is mainly determined by the Blanking time (100ns) and the response time of the hardware comparator (50ns).
picture3:triggerCBC After the duty cycle is limited
1. UCD3138 datasheet, Texas Instruments Inc., 2011
2. UCD31xx Central Interrupt Module (CIM) Programmer’s Manual, Texas Instruments Inc., 2011
3. UCD31xx Fusion Digital Power Peripherals Programmer’s Manual, Texas Instruments Inc., 2011
4. UCD31xx Miscellaneous Analog Control _MAC_, Texas Instruments Inc., 2011
The Links: LJ32H028 LQ104V1DG11