“This article demonstrates a method to efficiently bootstrap low voltage op amp buffers into high voltage buffers. ADI engineers took an op amp with excellent input characteristics and further improved its performance to better than the original op amp in terms of voltage range, gain accuracy, slew rate, and distortion.
Of course it is possible! You can take an op amp with excellent input characteristics and further improve its performance over the original op amp in terms of voltage range, gain accuracy, slew rate, and distortion.
Analog Devices engineers have designed the input of a precision voltmeter that requires a sub-picoamp input unity-gain amplifier/buffer with less than 1 μV pp of low frequency noise, an offset voltage as low as about 100 μV, and a nonlinearity error of less than 1 ppm. It also requires very low AC distortion at audio and 60 Hz in order to take advantage of the ever-increasing ADC resolution. This is ambitious enough, but it also requires buffering the ±40 V signal with a ±50V supply. The buffer input is connected to a high-impedance voltage divider, or directly to an external signal. Therefore, it must also be able to withstand the shock of electrostatic discharge and overvoltage input.
There are not many sub-picoamp bias current op amps available. Affordable devices are often referred to as electrometer-grade amplifiers, with bias currents as low as tens of femtoamps. Unfortunately, the low frequency voltage noise (0.1Hz to 10Hz) of these electrometer amplifiers is a few microvolts (peak-to-peak). In addition, its input offset voltage and offset temperature coefficient are generally not satisfactory. Its common-mode rejection ratio (CMRR) and open-loop gain are not good enough to support 1 ppm linearity. Finally, no electrometer can withstand high supply voltages.
The LTC6240 family offers 0.25 pA bias current (typ) and 0.55µV pp low frequency noise. This is good enough for an input buffer, but the device only supports supplies up to 12 V. ADI engineers would have to add circuitry around the amplifier to accommodate the higher voltage.
Figure 1 shows a schematic of the principle of the bootstrap amplifier.
Figure 1. Basic Bootstrap Power Supply Circuit Topology
The LTC6240 is powered by Vp (holding the output plus 5 V through a buffer amplifier with a gain of +1) and Vm (holding the output minus 5 V driven by another buffer).
Since the power supply always follows the input signal (buffered by the output of the LTC6240), there is ideally no common-mode input error at all. Even mediocre CMRR is boosted by at least 30 dB with bootstrapping. This 30 dB value is due to the finite gain accuracy of the Vp and Vm buffers.
The open-loop gain of the LTC6240 is similarly improved. Gain limitation occurs in amplifier circuits when there is a transistor output impedance between the internal gain node and the power supply rails. Since the power supply is bootstrapped to the output, very little signal current flows through the above impedance, and the increase in open-loop gain is similar to the increase in CMRR. However, the output load may still limit the open-loop gain.
Maybe not as obvious, but the overall slew rate of the circuit is also boosted by bootstrapping. Typically, it is limited by the LTC6240 internal quiescent current and supply-referenced compensation capacitors. When the power supply follows the input and output, there is very little dynamic current flowing into these capacitors and the amplifier does not go into a limited slew rate state. The buffer amplifier will eventually limit the overall slew rate.
The high voltage power supplies Vhvp and Vhvm may have interference, but the buffer output will suppress the interference to a large extent, and the power supply rejection ratio (PSRR) of the LTC6240 will be greatly enhanced.
So, that’s great; by bootstrapping the power supply, the buffer is improved in several ways. What might go wrong? The circuit shown in Figure 1 will almost certainly oscillate. The best way to think about the behavior of a power supply pin is to think of it as part of a feedback loop: the output pin voltage is multiplied by the buffer amplifier frequency response, which is then multiplied by 1/PSRR, added to the input, and finally multiplied by the open loop gain become the output, and so on. Figure 2a shows PSRR as a function of frequency.
Figure 2. (a) PSRR of LTC6240, (b) Open Loop Gain of LTC6240
No phase data is obtained in the PSRR curve, but it is assumed to have a +90° phase. Yes, this +90° is like a differentiator. As shown in Figure 2b, from low frequencies to 100 kHz, the open-loop gain has a -90° phase, after which this negative value becomes larger and larger. The buffer will have a finite frequency response and will also exhibit phase lag. Summing all the phase lags in the loop ensures that the feedback phase at some frequencies is a multiple of 0° or 360°. If the power loop gain in these phases is greater than unity, oscillation will occur. The PSRR amplitude drops to a low of 4 dB (attenuation = -4 dB → gain = 0.63, not dB), and it looks like the loop may never have enough gain to oscillate. This is most likely wrong, since PSRR applies to both Vp and Vs, whose PSRR gains add up to exceed 1 in magnitude. Additionally, the buffer may have some peaking, after which its gain rolls off at high frequencies, pushing the overall feedback magnitude above unity. The buffer has to drive slightly larger capacitance and will have more phase lag. Anyway, LTspice®The circuit simulation in , shows that large-signal oscillation occurs (the frequency response and nonlinearity of the LTC6240 are reflected in the macromodel).
Figure 3 shows the complete circuit.
Figure 3. Complete Circuit
Note that the 1000 pF bypass capacitor must be tightly connected to the LTC6240 supply pins. Op-amps have dozens of internal transistors, and in this amplifier, the transistors have Ft on the order of GHz. They are often connected to each other in feedback, and unless bypass capacitors are installed, they may oscillate on high AC impedance supplies. 1000 pF is enough to cancel these oscillations. If the supply bypass capacitance is desired to be much larger than any output load capacitance, at high frequencies voltage transitions on the load capacitance will cause current to flow to the supply rails and may modulate the supply voltage, causing oscillations through PSRR feedback. Therefore, the bypass capacitor reduces the power supply modulation at frequency, which is equivalent to reducing the feedback gain from the output to the power supply.
Swing these bypass capacitors requires a lot of current and must be bidirectional. Q5 and Q6 are emitter followers that drive the slew current of the bypass capacitor. Q3 and Q4 are bias diodes that set the Q5 and Q6 quiescent current. Q2 provides bias current for these diodes and Zener diode D1 (actually the parallel reference IC), which sets the positive supply voltage relative to the output. The collector of Q2 is the output of a current mirror biased by R9 between the high voltage rails. If the supply voltage is not constant, R9 can be replaced with two current sources.
Q7 to Q12 form Vm minus power drivers comparable to those previously described. Note that the zener voltage mismatch is intentional: Vp is 5V higher than input/output and Vm is 3V lower than input/output. This mismatch places the midpoint of the input voltage within the LTC6240’s supply-limited input range, optimizing the slew waveform.
Typically, the LTC6240’s supply current consumes Q5’s emitter current and essentially turns off Q6, so the Vp buffer output impedance is mostly R3. Therefore, the bandwidth of the supply feedback Vp path is approximately 1/ (2π × 100 Ω × 0.001 µF) = 1.6 MHz. This ensures that at frequencies of 10 MHz and above, where the open-loop phase of the LTC6240 develops towards oscillation, the Vp loop gain is much less than 1. The 100Ω resistor also eliminates the need for follower Q5 to directly drive the 1000 pF capacitor. Emitter-followers have output inductance that can resonate with capacitive loads, causing ringing or even oscillation.
After designing to bootstrap above 1.6 MHz to fail, the perfect behavior of the overall circuit degrades beyond about 100 kHz. If the output cannot follow the input exactly, the benefits of bootstrapping will be compromised. Rin with Cin limits the bandwidth to 100 kHz, which is part of the ADC follower buffer’s system antialiasing filter, which also attenuates radio interference and unsupported slew rates.
The circuit must be able to withstand any unrestricted slew input signal or ESD, so Rin is also used to limit the input fault current. The resistor has four sections in series in order to share the input overdrive and temporarily withstand 1 kV. Depending on the signal source and expected overload, the input resistance can be reduced.
There are protection diodes inside the LTC6240 to steer the input overvoltage current to Vp or Vm. The maximum fault current allowed into the LTC6240 input is 10 mA, but this current can be increased for short periods of time if there is surrounding circuitry that quickly shuts off the input fault. The intended application for this circuit is the SPDT relay, which connects the input of the buffer to the ÷10 network when not powered. When powered up, the relay is connected directly to the input. Therefore, when unpowered, the buffer is connected to a source impedance much greater than 10 kΩ, and the fault voltage and current are reduced by a magnitude comparable to the 10 mA continuous rating. The input range of the application is ±400 V with a fault tolerance of ±1000 V. This can only be done safely with two comparators, which detect input overvoltage and quickly release the relay. This can be done in 1 ms to 2 ms, allowing a transient input current of 100 mA that will not melt the LTC6240’s protection diodes.
Note that D3 to D6 are used to steer the input overload current to the Vhvp or Vhvm supply, which was previously steered to Vp or Vm by the LTC6240. These power supplies may not be able to absorb overload current because this current flows backwards relative to normal power supply operation. You will need to rely on a bypass capacitor large enough to safely maintain the supply voltage while waiting for the relay switch to decompress. For a 100 mA overload, a 100 μF capacitor will be required to keep the supply voltage change within 2 V for 2 ms.
High voltage signal source
When testing the lab prototype, ADI engineers realized that there was no signal generator to provide enough output voltage swing of any waveform to excite the circuit. There are signal generators that can generate various waveforms up to ±10 V pp. It is now necessary to design an amplifier that can clearly reproduce large amplitude waveforms. Figure 4 shows a high-voltage discrete implementation of a current feedback amplifier (CFA).
Figure 4. High Voltage Amplifier
CFAs (Current Feedback Amplifiers) have very high slew rates and typically wide bandwidths (at unity gain). However, since high voltage transistors are used, the bandwidth is moderate. High voltage transistors have higher parasitic capacitance and lower F compared to lower voltage typests.
There are a few things to note here. The circuit itself has no function of limiting current or limiting power consumption, so a sustained high load current of more than 10mA will burn out the output stage and possibly even more circuit stages. Also, it is best not to add more than 0.1µF bypass capacitors on high voltage supplies. If a large capacitor is used, a short circuit can cause a soldering effect. Because of this, ADI engineers had to add 100µF bypass capacitors on the high voltage supply to suppress second harmonic distortion. ADI engineers rocked the lab power supply up and down by hand to avoid hard switching on and off. Note that 50V will generate enough current to flow through the body to cause cardiac arrest. It is best to reduce the current limit of the high voltage supply to 60 mA. 50 V is high enough to be vigilant.
In Figure 4, the ADA4898 op amp controls the CFA, keeping its accuracy and distortion under control. CFAs generally have high DC errors and long settling times for high accuracy. Op amps solve these problems.
The positive input to the CFA is node n25 and the negative input is n5 (yes, that’s the input). Rff and Rgg themselves set the gain of the internal CFA to about 27. This high gain controls the op amp output swing to ±2 V. The CFA can be set to a higher gain to further reduce the burden on the control amplifier, but in doing so, the CFA will lose bandwidth and increase distortion. The overall gain is set to 20 by Rf and Rg. Ctweak and Ctweak2 work with Rf to remove the phase lag of the CFA from the overall feedback of the op amp above 215 kHz, thereby enhancing the stability of the op amp.
Tn13 is the CFA gain node driven by the current mirror involving Q1/Q2/Q20 and Q11/Q12/Q19.
Q7/Q8/Q10/Q13 form an output buffer that acts as a composite complementary emitter follower. No current limiting circuit – do not short the output to anything!
The CFA section of the high voltage amplifier has a -3 dB bandwidth of 35 MHz and does not peak itself. The -3 dB bandwidth of the overall circuit is 33 MHz, but there is 8 dB of peaking. Typically, the bandwidth of the second amplifier of the composite amplifier design is at least 3 times the bandwidth of the input control amplifier to avoid peaking, but such favorable ratios cannot be obtained. At least the 8 dB peak doesn’t have a high Q, and the ringing fades away fairly quickly. Below the peaking frequency, the target 100 kHz signal is reproduced well. At 100 kHz and an output of 80 V pp, the distortion measures -82dBc; below 100 kHz and an output of 32 V pp, the distortion drops to -100 dBc. For fast edges, the square wave response has about 60% overshoot; when the output slew rate is less than 250 V/µs, there is little or no overshoot. The maximum slew rate is approximately 1900 V/µs.
How to measure ±40 V output with common lab equipment in the face of large signals? Neither the high-voltage amplifier nor the high-voltage buffer should output more than 10 mA, and neither can they drive 40 pF loads stably. Coaxial cable has a permittivity of 27 pF/ft, which is too much capacitance. The oscilloscope ÷ 10 probe only has about 15 pF||10MΩ load, so coupling to the oscilloscope will be fine.
For distortion measurements, none of the audio analyzers in the lab can achieve -80 dBc at 100 kHz, so a spectrum analyzer must be turned to. Unfortunately, the spectrum analyzer only has a 50Ω input, which is too low for the driver circuit. The solution is to raise the impedance to 50Ω (see Figure 5); that is, place a 5 kΩ voltage divider between the signal and the 50Ω analyzer input, making a voltage divider close to ÷100. Importantly, the 5 kΩ resistors do not exhibit thermal offsets with low frequency signals because these offsets are related to VOUT2Correlation will cause even harmonics. ADI engineers chose to make the Rdivider by connecting five 1kΩ, 2W resistors in series. A 2 W resistor has a thermal resistance of about 37°C/W, and five 1 kΩ resistors have a thermal resistance of 7.5°C/W. When a ±40 V sine wave is applied to it, the power dissipation is 160 mW, and resistance heating will cause a temperature increase of 7.5 × 0.16 = 1.2 °C in the resistance. The resistor offset is about 100 ppm/°C, so there is a 120 ppm offset at dc, or about 0.01% nonlinearity error and -80 dBc distortion. How can this precision be sufficient for measurement? The good news is that the thermal time constant of the voltage divider resistors is quite large, and ADI engineers expect the actual resistance shift to be small in the middle of the 100 kHz cycle. Ironically, the distortion is worse at lower frequencies (probably 1 kHz and below).
Due to the limited analyzer input range, the 80 V pp signal must be attenuated anyway, but it is still too large for optimal spectrum analyzer performance. Unassisted, the analyzer can only provide -80 dBc distortion, which is a trade-off of either its noise overwhelms the harmonics or the large input causing additional distortion. The solution is to place a 100 kHz trap at the analyzer input to cancel the fundamental amplitude. When the signal is less than a few millivolts (harmonics only), a measurement range close to -120 dBc can be achieved. Figure 5 shows the test setup.
Figure 5. Distortion Test Setup
The generator drives Rterm through a low-pass filter (Linput and Cinput) that attenuates the generator’s 100 kHz harmonics. The distortion is thus improved to -113 dBc, which is lower than the circuit to be measured. The cleaned signal is boosted by a high voltage amplifier and passed by a buffer, which drives a voltage divider.
The Inductor consists of magnet wire wound around a large spool (for the power EI core). Due to the added distortion, no core material of any kind can be used; air-wound must be used. Just wrap and measure repeatedly.
The Ltrap magnetically radiates harmonics to adjacent loose unshielded lines (this is the usual method), so place the trap element in a cookie jar with a grounded BNC jack connection. There are cookie jars in the lab, any shielded steel box will do.
For calibration, ADI engineers replaced the two amplifiers with thru-wires and recorded the gain from the Rterm voltage to the input of the spectrum analyzer at the second to fourth harmonic frequencies. When measuring harmonics in a distortion test, ADI engineers use the stored gain for that frequency to infer the harmonic content at the output of the buffer. ADI engineers monitor the amplitude of the buffer’s fundamental output with an oscilloscope, calculate the rms value of the normalized harmonics, and divide by the fundamental amplitude to get the overall distortion.
Using the setup shown in Figure 5, the spectrum analyzer has a distortion of -81 dBc at 70 V pp and 80 V pp output, -82 dBc at 50 V pp and 60 V pp output, and at 16 V pp and 32 V Distortion at pp output is -86.5 dBc, both at 100 kHz.
Then measure DC linearity, gain accuracy, and input range. Figure 6 shows the input offset of the buffer when sweeping the input DC signal.
Any amplifier with useful input characteristics can be bootstrapped as described above to operate with high voltage signals. Ultra-low input noise or ultra-low offset amplifiers can operate at hundreds of volts.
Figure 6. Buffer VOS with VIN Relationship. Rl = 50 kΩ and ∞.
Multimeters have difficulty resolving sub-microvolt changes in the context of ±40 V signals, but since this is a buffer, ADI engineers can simply connect a voltmeter from input to output to find the offset, and use a sensitive range. The common-mode rejection of this multimeter is less than 1 μV for ±40 V inputs (input shorted for this test).
The disturbances in the curve are caused by low frequency noise, especially thermal disturbances. The presence of someone nearby or an air conditioner can cause airflow and thermal changes that can cause Seebeck and thermocouple voltage errors in the order of microvolts in the circuit. Since there is no well shielded room, but cover the circuit with some clothing to prevent draft effects. Even so, the result has a drift of 0.6µV rms.
In noise, the no-load (green) curve shows a gain error of about 0.03 ppm. Not bad. The unbootstrapped LTC6240 has a nominal gain error of 5.6 ppm and a worst-case gain error of 100 ppm due to CMRR error. When loaded with 50 kΩ (purple), a gain error of -0.38ppm is seen. This load gain error corresponds to an output impedance of 0.02Ω. It’s hard to know where the 0.02Ω is coming from – it could be load current modulating Vp or Vm and acting through a common mode rejection or gain limiting process within the LTC6240, or it could just be wire and board resistance. However, to keep the gain accurate, the feedback of the LTC6240 can be connected remotely to the final load, forming a Kelvin connection. Figure 7 shows the small signal impulse response.
Figure 7. Small Signal Impulse Response
The ringing in the green channel is actually the output of the high voltage amplifier. It’s not ringing on its own, simply because the scope probes and board-to-board grounds used are mediocre. The yellow channel is the buffer output, which is a simple exponential image dominated by Cin + Rin.
Figure 8 shows the large-signal impulse response with an input slew rate of ±32 V/µs—a nice, smooth response.
Figure 8. Large Signal Response to Moderate Input Slew Rate (±32 V/µs)
Figure 9 shows the buffer response to overload slew rate. An 80 V pp output at 100 kHz requires a peak slew rate of ±25 V/µs, which is within the ±32 V/µs capability shown.
Figure 9. Large Signal Response to Overload Input Slew Rate (±130 V/μs)
Note that the input filter limits the overload slew rate to what the buffer can handle. Ripple is an artifact of the bootstrap circuit’s inability to follow the output slew, which causes the input headroom to repeatedly overload during slew. Decreasing Cin will force the input slew rate to be larger and the bootstrap circuit will not be able to follow, resulting in more ugly ripples.
This article demonstrates a method to efficiently bootstrap low voltage op amp buffers into high voltage buffers. ADI engineers took an op amp with excellent input characteristics and further improved its performance to better than the original op amp in terms of voltage range, gain accuracy, slew rate, and distortion. What are your opinions on this method? Leave a message at the end of the article, let’s discuss together~