Chips continue to be miniaturized, and the manufacturing process is advancing towards smaller 5nm and 3nm. Moore’s Law has been repeatedly passed to the end, and chip packaging technology is generally considered to be an important development direction of semiconductor technology in the next stage.
Dr. Yu Daquan, Distinguished Professor of Xiamen University and founder of Yuntian Semiconductor, once pointed out that as the development of Moore’s Law slows down, using advanced packaging technology to meet system miniaturization and multi-function has become a new engine for the development of the integrated circuit industry. Packaging technology came into being with the invention of integrated circuits, and its main functions are to complete power distribution, signal distribution, heat dissipation and physical protection. With the development of chip technology, packaging is constantly innovating, and the supply chain is facing a big test.
1. The heroes compete for advanced packaging
Advanced packaging technology can relatively easily achieve high-density integration of chips, miniaturization of volume, and lower cost, which is in line with the trend of high-end chips evolving towards smaller size, higher performance, and lower power consumption.
Especially high-density advanced packaging (HDAP) such as CoWoS (Chip On Wafer On Substrate), FOWLP (fan-out wafer level packaging) and WoW, which have shown great advantages in improving chip performance, have successfully attracted major mainstream chip manufacturers. The attention of packaging and testing, foundry and design manufacturers has begun to continue to invest in this field.
For example, CoWoS, which is a 2.5D packaging technology introduced by TSMC, is called wafer-level packaging. CoWoS is aimed at the high-end market, and the number of connections and package size are relatively large.
Since mass production of CoWoS began in 2012, TSMC has packaged multiple chips together through this packaging method of sharing substrates between chips, and the bare chips on the plane are interconnected through Silicon Interposer, which achieves small package size and high transmission speed. High, low power consumption, the effect of less pins. Also, FOWLP, a technology predicted to be the basis of next-generation compact, high-performance Electronic devices. According to Yole data, the total global output value of FOWLP is expected to exceed 2.3 billion US dollars in 2022, and the CAGR (compound annual growth rate) between 2019 and 2022 will be close to 20%.
It is reported that the first generation of fan-out packaging uses Infineon’s embedded wafer-level ball gate array (eWLB) technology, which was launched by Freescale (now NXP) in 2009. However, integrated fan-out packaging (InFO) was only produced by TSMC before this. TSMC’s InFO technology is the most striking example of high-density fan-out, and Samsung Electronics’ System LSI Division believes that it is this technology that led TSMC to grab Apple’s (Apple) A10 processor foundry orders. For this reason, Samsung Electro-Mechanics (Semco) stepped into the semiconductor packaging market and cooperated with Samsung Electronics to develop FOWLP technology, with a view to fully confronting TSMC in the new round of customer order competition.
According to Techsearch International, these HDAP technologies are driving the industry’s need for device-package co-design and new processes. At present, foundries have begun to use part of their limited production capacity for advanced packaging and testing, and traditional packaging and testing manufacturers are gradually upgrading to advanced packaging and testing. Although so far, foundries and packaging and testing manufacturers have not completely crossed businesses, and they are fighting independently in their respective fields. But in the future, the two sides will definitely enter more and more overlapping fields, and advanced packaging will become a battleground for military strategists.
2. HDAP, it’s not easy to say I love you
However, there are still some challenges to achieve something similar to HDAP.
Data show that, first of all, HDAP is heterogeneous. Even if upstream EDA vendors have modified traditional tools to handle a variety of new technologies, these new technologies also require physical verification, such as design rule checking (DRC), layout and schematic comparison (LVS) and so on. In HDAP, the connection must be made through an interposer or some type of interconnection technology, in which case it affects the interconnection characteristics of the system, and these characteristics also affect each other, while affecting manufacturability characteristic design.
Second, the new HDAP technology requires the design team to work together to optimize the entire system, not just individual components. Increased engineering costs due to issues such as chip and package/interposer misalignment, connection errors between components and pads; manufacturing delays due to quality or errors in manufacturing data; and poor signal and power integrity performance, 2.5 Problems such as functional failures caused by unqualified thermal stability of D assembly.
Furthermore, HDAP also significantly increases the design complexity, needing to describe all interconnections from chip to substrate, from interposer to substrate, substrate to circuit board, and substrate to test board. This is very difficult to control in the traditional packaging industry. At present, many of them have to be integrated manually, with some piecemeal inspections.
As a new direction, HDAP has also begun to affect the design process of semiconductors. These new technologies enable partitioning of the overall design, like an interconnect with features on the outside of the chip that are very similar to the inside of the chip. Advanced packaging enables manufacturers to integrate different technologies (processes), but it also brings related challenges to traditional design tools.
On this basis, the traditional packaging design can no longer meet the changing needs of the market. How to efficiently complete the design and get it verified will bring new challenges to EDA tools. The market urgently needs new and more efficient processes, methods and design tools.
3. Mentor’s weapon
Mentor is an EDA manufacturer that pays great attention to advanced packaging technology. Lincoln Lee, technical director of Mentor Asia Pacific, mentioned that as an EDA manufacturer, its products run through all aspects of design and packaging.
As early as more than 10 years ago (2007), Mentor saw potential opportunities in the packaging market and began to design solutions for leading customers. He emphasized that the semiconductor industry is developing rapidly, and advanced packaging is gradually becoming the main force. If it cannot quickly adapt to customer requirements, it will be left behind. It is a win-win for Mentor and its customers to make efforts in the field of advanced packaging.
In 2013, Mentor officially launched the Xpedition Package Integrator (XPI) high-density advanced packaging (HDAP) process, which is the industry’s first comprehensive solution for today’s advanced IC package design and verification.
According to the data, XPI products already have a high degree of integration, but based on the need for division of labor in the entire design process, Mentor splits the two functions of XPI into Xpedition Substrate Integrator tool and Xpedition Package Designer technology. The unique Xpedition Substrate Integrator (xSI) tool enables rapid definition and optimization of heterogeneous substrate package assemblies. New Xpedition Package Designer (xPD) technology implemented for physical packaging ensures that design signoff and verified data are synchronized. Caliber 3D Stack technology can perform complete Signoff DRC/LVS verification for various 2.5D and 3D stacked chip components.
In the process of continuous optimization, Xpedition can work with multiple people without splitting and avoiding multiple merging, so as to maximize team work efficiency. At present, Mentor is trying its best to solve the power consumption, heat dissipation and performance problems of multi-chip packaging. Lincoln explained that everyone wants to “squeeze” more functions into the same chip, but putting so many high-performance chips together will generate extremely high heat density. Therefore, thermal analysis is a very critical step.
At present, the number of companies making chips is decreasing, largely due to the high cost of advanced technology ranks, so advanced design tools are particularly important. Lincoln mentioned that Mentor’s advantage is that it has a very comprehensive process. The new solution can provide convenience for IC design manufacturers and meet their needs to a certain extent.
4. Mentor and China
Now, many manufacturers in the Chinese mainland market have begun to pay attention to advanced packaging, especially packaging and testing companies. In recent years, overseas mergers and acquisitions have allowed Chinese packaging and testing companies to quickly acquire technology and markets, make up for some structural defects, and greatly promote the upward development of China’s packaging and testing industry.
According to data from the China Semiconductor Association, the scale of the packaging and testing market in mainland China has increased from 103.4 billion yuan in 2012 to 219.6 billion yuan in 2018. In the packaging and testing market in 2019, mainland China accounted for 28%, second only to Taiwan, China.
Lincoln pointed out that as early as 1989, Mentor had already entered mainland China. Although the market was mainly based on PCB board-level design at that time, the domestic IC industry in mainland China was still in its infancy, and the overall market size was not as large as it is now, Mentor did not underestimate the Chinese market and its future development potential at all. In addition, Mentor also cooperates with local governments, incubation platforms, universities and research institutes to reduce the cost of innovation and entrepreneurship, and actively supports future star enterprises.
Over the years, Mentor has witnessed the growing strength of China’s domestic IC industry, especially in the field of packaging and testing. Lincoln said that in recent years, China’s local advanced packaging and testing manufacturers have basically formed the industrialization capability of advanced packaging through independent research and development and mergers and acquisitions. However, in terms of the proportion of advanced packaging revenue to total revenue and the development of advanced packaging technologies such as high-density integration However, there is still a certain gap between China’s overall advanced packaging technology level and the international leading level.
On this basis, Mentor is continuously supporting the development of Chinese manufacturers in the field of advanced packaging, helping Chinese manufacturers improve performance and power consumption. At the same time, Lincoln also mentioned that among chips of the same level, heterogeneous integration can help optimize the performance of products using the Mentor HDAP design environment.
In 2020, the battle surrounding advanced packaging continues to escalate, and advanced chip manufacturers are constantly increasing their efforts to explore a broader space for chip innovation. Although the core details of these technical methods are different, everyone’s strategy is to continuously increase chip density and realize more complex and flexible system-on-chips to meet customers’ increasingly rich application needs.
As the manufacturing process approaches the limit and the cost increases infinitely, Mentor will play an increasingly important and indispensable role with its rich experience in this field.
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